Lines Matching refs:TryCand
143 SISchedulerCandidate &TryCand,
147 TryCand.Reason = Reason;
160 SISchedulerCandidate &TryCand,
164 TryCand.Reason = Reason;
193 SISchedCandidate &TryCand) {
196 TryCand.Reason = NodeOrder;
201 tryLess(TryCand.SGPRUsage, Cand.SGPRUsage, TryCand, Cand, RegUsage))
219 if (tryLess(TryCand.HasLowLatencyNonWaitedParent,
221 TryCand, Cand, SIScheduleCandReason::Depth))
224 if (tryGreater(TryCand.IsLowLatency, Cand.IsLowLatency,
225 TryCand, Cand, SIScheduleCandReason::Depth))
228 if (TryCand.IsLowLatency &&
229 tryLess(TryCand.LowLatencyOffset, Cand.LowLatencyOffset,
230 TryCand, Cand, SIScheduleCandReason::Depth))
233 if (tryLess(TryCand.VGPRUsage, Cand.VGPRUsage, TryCand, Cand, RegUsage))
237 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
238 TryCand.Reason = NodeOrder;
246 SISchedCandidate TryCand;
250 TryCand.SU = SU;
252 TryCand.SGPRUsage = pressure[DAG->getSGPRSetID()];
253 TryCand.VGPRUsage = pressure[DAG->getVGPRSetID()];
254 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum];
255 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum];
256 TryCand.HasLowLatencyNonWaitedParent =
258 tryCandidateTopDown(TopCand, TryCand);
259 if (TryCand.Reason != NoCand)
260 TopCand.setBest(TryCand);
1410 SIBlockSchedCandidate &TryCand) {
1412 TryCand.Reason = NodeOrder;
1417 if (tryLess(TryCand.LastPosHighLatParentScheduled,
1418 Cand.LastPosHighLatParentScheduled, TryCand, Cand, Latency))
1421 if (tryGreater(TryCand.IsHighLatency, Cand.IsHighLatency,
1422 TryCand, Cand, Latency))
1424 if (TryCand.IsHighLatency && tryGreater(TryCand.Height, Cand.Height,
1425 TryCand, Cand, Depth))
1427 if (tryGreater(TryCand.NumHighLatencySuccessors,
1429 TryCand, Cand, Successor))
1435 SIBlockSchedCandidate &TryCand) {
1437 TryCand.Reason = NodeOrder;
1441 if (tryLess(TryCand.VGPRUsageDiff > 0, Cand.VGPRUsageDiff > 0,
1442 TryCand, Cand, RegUsage))
1444 if (tryGreater(TryCand.NumSuccessors > 0,
1446 TryCand, Cand, Successor))
1448 if (tryGreater(TryCand.Height, Cand.Height, TryCand, Cand, Depth))
1450 if (tryLess(TryCand.VGPRUsageDiff, Cand.VGPRUsageDiff,
1451 TryCand, Cand, RegUsage))
1485 SIBlockSchedCandidate TryCand;
1486 TryCand.Block = *I;
1487 TryCand.IsHighLatency = TryCand.Block->isHighLatencyBlock();
1488 TryCand.VGPRUsageDiff =
1489 checkRegUsageImpact(TryCand.Block->getInRegs(),
1490 TryCand.Block->getOutRegs())[DAG->getVGPRSetID()];
1491 TryCand.NumSuccessors = TryCand.Block->getSuccs().size();
1492 TryCand.NumHighLatencySuccessors =
1493 TryCand.Block->getNumHighLatencySuccessors();
1494 TryCand.LastPosHighLatParentScheduled =
1496 LastPosHighLatencyParentScheduled[TryCand.Block->getID()] -
1498 TryCand.Height = TryCand.Block->Height;
1502 if (!tryCandidateRegUsage(Cand, TryCand) &&
1504 tryCandidateLatency(Cand, TryCand);
1506 if (!tryCandidateLatency(Cand, TryCand))
1507 tryCandidateRegUsage(Cand, TryCand);
1509 if (TryCand.Reason != NoCand) {
1510 Cand.setBest(TryCand);
