Lines Matching refs:ARM
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
27 #include "ARM.h"
56 return "ARM A15 S->D optimizer";
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
149 &ARM::DPRRegClass);
150 if (DReg != ARM::NoRegister) return ARM::ssub_1;
151 return ARM::ssub_0;
161 if (!MI) return ARM::ssub_0;
165 if (!MO) return ARM::ssub_0;
168 &ARM::SPRRegClass)) {
173 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
174 return ARM::ssub_0;
272 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
296 &ARM::SPRRegClass)) {
334 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
338 &ARM::SPRRegClass))
341 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
415 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
416 !usesRegClass(MO, &ARM::QPRRegClass) &&
417 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
430 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
431 &ARM::DPRRegClass);
435 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
462 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
468 .addImm(ARM::dsub_0)
470 .addImm(ARM::dsub_1);
480 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
484 TII->get(ARM::VEXTd32), Out)
494 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
510 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
531 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
532 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
534 ARM::dsub_0, &ARM::DPRRegClass);
536 ARM::dsub_1, &ARM::DPRRegClass);
548 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
554 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
560 case ARM::ssub_0: Lane = 0; break;
561 case ARM::ssub_1: Lane = 1; break;
566 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
567 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
