Lines Matching defs:Add
1026 setTargetDAGCombine(ISD::ADD);
1536 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1572 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1723 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1743 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1745 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1928 // Add argument registers to the end of the list so that they are known live
1934 // Add a register mask operand representing the call-preserved registers.
2634 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2651 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2664 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2760 // The address of the thread local variable is the add of the thread
2762 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3165 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3531 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3536 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3994 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4125 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
4140 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
4339 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4595 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4648 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
4660 // Gather the #bits with vpaddl (pairwise add.)
4691 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4710 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4768 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5901 // Add this element source to the list if it's not already there.
6524 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
6547 /// reach a total size of 64 bits. We have to add the extension separately
6572 /// before extension is less than 64 bits we add a an extension to resize
6615 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6626 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6733 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6771 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6876 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6882 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6978 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet,
6980 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
7320 // add r5, pc
7344 // add r1, pc
7347 // add r2, $jbuf, #+4 ; &jbuf[1]
7379 // add r1, pc, r1
7498 // Add a register mask with no preserved registers. This results in all
7711 // Add the jump table entries as successors to the MBB.
8105 // Add epilogue to handle BytesLeft.
8539 // Add the optional cc_out operand
8655 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8666 // (add (zext cc), x) -> (select cc (add x, 1), x)
8667 // (add (sext cc), x) -> (select cc (add x, -1), x)
8717 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
8739 // index such that we have a pair wise add pattern.
8748 // For each operands to the ADD which are BUILD_VECTORs,
8821 // Look for multiply add opportunities.
8822 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8823 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8824 // a glue link from the first add to the second add.
9041 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
9049 // Attempt to create vpaddl for this add.
9053 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
9060 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
9116 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
9119 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
9170 // (mul x, 2^N + 1) => (add (shl x, N), x)
9171 Res = DAG.getNode(ISD::ADD, DL, VT,
9198 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
9199 Res = DAG.getNode(ISD::ADD, DL, VT,
9216 // Do not add new nodes to DAG combiner worklist.
9391 // Do not add new nodes to DAG combiner worklist.
9417 // Do not add new nodes to DAG combiner worklist.
9433 // Do not add new nodes to DAG combiner worklist.
9453 // Do not add new nodes to DAG combiner worklist.
9638 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9910 if (User->getOpcode() != ISD::ADD ||
9914 // Check that the add is independent of the load/store. Otherwise, folding
9998 // OK, we found an ADD we can fold into the base update.
10060 // so just add all but the alignment operand.
10316 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
10339 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
11035 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
11211 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
11439 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
11440 /// *or sub* immediate, that is the target has add or sub instructions which can
11441 /// add a register with the immediate without having to materialize the
11444 // Same encoding for add/sub, just flip the sign.
11458 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
11467 assert(Ptr->getOpcode() == ISD::ADD);
11473 isInc = (Ptr->getOpcode() == ISD::ADD);
11481 assert(Ptr->getOpcode() == ISD::ADD);
11489 if (Ptr->getOpcode() == ISD::ADD) {
11503 isInc = (Ptr->getOpcode() == ISD::ADD);
11517 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
11524 assert(Ptr->getOpcode() == ISD::ADD);
11529 isInc = Ptr->getOpcode() == ISD::ADD;
11615 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
11841 /// vector. If it is invalid, don't add anything to Ops.
11878 // This must be a constant between 0 and 255, for ADD
11897 // This must be a constant between -255 and -1, for negated ADD
11942 // for 3-operand ADD/SUB immediate instructions.
11967 // ADD sp + immediate.
11990 // ADD/SUB sp = sp + immediate.
12373 // FIXME: add a comment with a link to documentation justifying this.
