Lines Matching defs:CC
71 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
74 : CCState(CC, isVarArg, MF, locs, C) {
261 const CallingConv::ID CC;
349 setLibcallCallingConv(LC.Op, LC.CC);
360 const CallingConv::ID CC;
372 setLibcallCallingConv(LC.Op, LC.CC);
383 const CallingConv::ID CC;
397 setLibcallCallingConv(LC.Op, LC.CC);
1328 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1329 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1330 switch (CC) {
1345 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1346 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1349 switch (CC) {
1384 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1386 switch (CC) {
1392 return CC;
1422 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1425 switch (getEffectiveCallingConv(CC, isVarArg)) {
3421 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3428 switch (CC) {
3433 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3440 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3447 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3454 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3462 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3648 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3652 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3653 CC == ISD::SETULE)
3657 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3658 CC == ISD::SETULT)
3663 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3664 CC == ISD::SETULT)
3675 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3676 CC == ISD::SETUGT) {
3684 if (CC == ISD::SETO) {
3691 if (CC == ISD::SETUNE) {
3723 static bool isGTorGE(ISD::CondCode CC) {
3724 return CC == ISD::SETGT || CC == ISD::SETGE;
3727 static bool isLTorLE(ISD::CondCode CC) {
3728 return CC == ISD::SETLT || CC == ISD::SETLE;
3731 // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
3739 const ISD::CondCode CC, const SDValue K) {
3740 return (isGTorGE(CC) &&
3742 (isLTorLE(CC) &&
3749 const ISD::CondCode CC, const SDValue K) {
3750 return (isGTorGE(CC) &&
3752 (isLTorLE(CC) &&
3863 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3868 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3875 CC = ISD::SETNE;
3892 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3895 CC = ISD::getSetCCInverse(CC, true);
3902 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3907 FPCCToARMCC(CC, CondCode, CondCode2);
3914 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4012 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4026 if (CC == ISD::SETOEQ)
4027 CC = ISD::SETEQ;
4028 else if (CC == ISD::SETUNE)
4029 CC = ISD::SETNE;
4038 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4050 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4062 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4069 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4076 CC = ISD::SETNE;
4082 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4091 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4092 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4098 FPCCToARMCC(CC, CondCode, CondCode2);
4878 SDValue CC = Op.getOperand(2);
4881 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
6961 CallingConv::ID CC = getLibcallCallingConv(LC);
6967 .setCallee(CC, RetTy, Callee, std::move(Args))
8449 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
8593 // Detects these expressions where cc is an i1 value:
8595 // (select cc 0, y) [AllOnes=0]
8596 // (select cc y, 0) [AllOnes=0]
8597 // (zext cc) [AllOnes=0]
8598 // (sext cc) [AllOnes=0/1]
8599 // (select cc -1, y) [AllOnes=1]
8600 // (select cc y, -1) [AllOnes=1]
8602 // Invert is set when N is the null/all ones constant when CC is false.
8605 SDValue &CC, bool &Invert,
8611 CC = N->getOperand(0);
8627 // (zext cc) can never be the all ones value.
8634 CC = N->getOperand(0);
8635 if (CC.getValueType() != MVT::i1)
8655 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8656 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8657 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
8658 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8659 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8666 // (add (zext cc), x) -> (select cc (add x, 1), x)
8667 // (add (sext cc), x) -> (select cc (add x, -1), x)
8690 // Slct is now know to be the desired identity constant when CC is true.
8694 // Unless SwapSelectOps says CC should be false.
9053 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
9083 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
9255 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
9297 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
9470 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
10830 auto CC = CCNode->getAPIntValue().getLimitedValue();
10846 if (CC == ARMCC::EQ) {
10851 assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?");
10919 ARMCC::CondCodes CC =
10922 // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
10923 // -> (brcond Chain BB CC CPSR Cmp)
10924 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
10959 ARMCC::CondCodes CC =
10987 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
10990 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10997 // (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
10998 // -> (cmov F T CC CPSR Cmp)
10999 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
11834 if (StringRef("{cc}").equals_lower(Constraint))
