Lines Matching refs:Lower
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
905 // We want to custom lower some of our intrinsics.
1443 /// LowerCallResult - Lower the result values of a call into the
1779 // For tail calls lower the arguments to the 'real' stack slot.
2469 // and pass the lower and high parts through.
2667 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2708 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2925 default: return SDValue(); // Don't custom lower most intrinsics.
3731 // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
3815 // Figure out which conditional is saturating the lower/upper bound.
3830 // Check that the constant in the lower-bound check is
4515 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4551 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4805 // Lower vector shifts on NEON to use VSHL.
4843 "Unknown shift to lower!");
4845 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4852 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5156 // swap higher and lower 32 bit word
5198 // possible. Lower it to a splat followed by an extract.
5392 // upper and lower parts of the mask with a matching value for WhichResult
5819 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
7058 SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
7063 Results.push_back(Lower);
7142 default: llvm_unreachable("Don't know how to custom lower this!");
7223 llvm_unreachable("Don't know how to custom lower this!");
10557 // Vector shifts: check for immediate versions and lower them.
11710 // At this point, we have to lower this constraint to something else, so we
11711 // lower it to an "r" or "w". However, by doing this we will force the result
11840 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12107 // Lower call
12464 // If the index is unknown at compile time, this is very expensive to lower
12565 /// \brief Lower an interleaved load into a vldN intrinsic.
12567 /// E.g. Lower an interleaved load (Factor = 2):
12649 /// \brief Lower an interleaved store into a vstN intrinsic.
12651 /// E.g. Lower an interleaved store (Factor = 3):
