Lines Matching refs:Op
175 const RTLIB::Libcall Op;
235 setLibcallName(LC.Op, LC.Name);
237 setCmpLibcallCC(LC.Op, LC.Cond);
259 const RTLIB::Libcall Op;
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
351 setCmpLibcallCC(LC.Op, LC.Cond);
358 const RTLIB::Libcall Op;
371 setLibcallName(LC.Op, LC.Name);
372 setLibcallCallingConv(LC.Op, LC.CC);
374 setCmpLibcallCC(LC.Op, LC.Cond);
381 const RTLIB::Libcall Op;
396 setLibcallName(LC.Op, LC.Name);
397 setLibcallCallingConv(LC.Op, LC.CC);
2470 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2471 SDLoc DL(Op);
2472 SDValue WriteValue = Op->getOperand(2);
2482 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2492 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2493 EVT PtrVT = Op.getValueType();
2495 SDLoc dl(Op);
2496 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2511 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2516 SDLoc DL(Op);
2518 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2567 ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2570 SDLoc DL(Op);
2574 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2609 ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2615 SDLoc DL(Op);
2655 const auto *GA = cast<GlobalAddressSDNode>(Op);
2766 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2768 return LowerGlobalTLSAddressDarwin(Op, DAG);
2771 return LowerGlobalTLSAddressWindows(Op, DAG);
2775 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2792 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2795 SDLoc dl(Op);
2796 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2805 SDLoc dl(Op);
2845 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2848 SDLoc dl(Op);
2849 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2869 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2875 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2880 SDLoc DL(Op);
2897 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2898 SDLoc dl(Op);
2901 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2902 Op.getOperand(1), Val);
2906 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2907 SDLoc dl(Op);
2908 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2909 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
2912 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
2914 SDLoc dl(Op);
2916 Op.getOperand(0));
2920 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2922 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2923 SDLoc dl(Op);
2927 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2929 return DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, Op.getOperand(1));
2963 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2964 Op.getOperand(1), Op.getOperand(2));
2970 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2971 Op.getOperand(1), Op.getOperand(2));
2975 if (Op.getValueType().isFloatingPoint())
2979 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2980 Op.getOperand(1), Op.getOperand(2));
2985 if (!Op.getValueType().isFloatingPoint()) {
2988 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2989 Op.getOperand(1), Op.getOperand(2));
2993 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2994 Op.getOperand(1), Op.getOperand(2));
2999 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3002 SDLoc dl(Op);
3009 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3013 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3027 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3032 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3038 return Op.getOperand(0);
3040 SDLoc dl(Op);
3041 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3045 return Op.getOperand(0);
3047 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3054 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3055 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3059 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3065 SDLoc dl(Op);
3068 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3069 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3396 static bool isFloatingPointZero(SDValue Op) {
3397 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3399 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3401 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3402 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3407 } else if (Op->getOpcode() == ISD::BITCAST &&
3408 Op->getValueType(0) == MVT::f64) {
3411 SDValue BitcastOp = Op->getOperand(0);
3512 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3514 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3517 SDValue LHS = Op.getOperand(0);
3518 SDValue RHS = Op.getOperand(1);
3519 SDLoc dl(Op);
3526 switch (Op.getOpcode()) {
3531 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3536 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3541 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3546 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3556 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3558 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3563 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3565 SDLoc dl(Op);
3569 EVT VT = Op.getValueType();
3574 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3579 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3580 SDValue Cond = Op.getOperand(0);
3581 SDValue SelectTrue = Op.getOperand(1);
3582 SDValue SelectFalse = Op.getOperand(2);
3583 SDLoc dl(Op);
3596 EVT VT = Op.getValueType();
3628 EVT VT = Op.getValueType();
3769 static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
3772 SDValue LHS1 = Op.getOperand(0);
3773 SDValue RHS1 = Op.getOperand(1);
3774 SDValue TrueVal1 = Op.getOperand(2);
3775 SDValue FalseVal1 = Op.getOperand(3);
3776 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3818 ? &Op
3823 ? &Op
3837 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
3849 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3851 EVT VT = Op.getValueType();
3852 SDLoc dl(Op);
3857 if (isSaturatingConditional(Op, SatValue, SatConstant))
3861 SDValue LHS = Op.getOperand(0);
3862 SDValue RHS = Op.getOperand(1);
3863 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3864 SDValue TrueVal = Op.getOperand(2);
3865 SDValue FalseVal = Op.getOperand(3);
3940 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3942 SDNode *N = Op.getNode();
3948 EVT VT = Op.getValueType();
3954 if (isFloatingPointZero(Op)) {
3961 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3962 if (isFloatingPointZero(Op))
3963 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
3965 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3966 return DAG.getLoad(MVT::i32, SDLoc(Op),
3974 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3976 SDLoc dl(Op);
3978 if (isFloatingPointZero(Op)) {
3984 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4010 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4011 SDValue Chain = Op.getOperand(0);
4012 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4013 SDValue LHS = Op.getOperand(2);
4014 SDValue RHS = Op.getOperand(3);
4015 SDValue Dest = Op.getOperand(4);
4016 SDLoc dl(Op);
4060 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4061 SDValue Chain = Op.getOperand(0);
4062 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4063 SDValue LHS = Op.getOperand(2);
4064 SDValue RHS = Op.getOperand(3);
4065 SDValue Dest = Op.getOperand(4);
4066 SDLoc dl(Op);
4093 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4114 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4115 SDValue Chain = Op.getOperand(0);
4116 SDValue Table = Op.getOperand(1);
4117 SDValue Index = Op.getOperand(2);
4118 SDLoc dl(Op);
4132 Addr, Op.getOperand(2), JTI);
4152 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4153 EVT VT = Op.getValueType();
4154 SDLoc dl(Op);
4156 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4157 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4158 return Op;
4159 return DAG.UnrollVectorOp(Op.getNode());
4162 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
4165 return DAG.UnrollVectorOp(Op.getNode());
4167 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
4168 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4171 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4172 EVT VT = Op.getValueType();
4174 return LowerVectorFP_TO_INT(Op, DAG);
4175 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4177 if (Op.getOpcode() == ISD::FP_TO_SINT)
4178 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4179 Op.getValueType());
4181 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4182 Op.getValueType());
4183 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4184 /*isSigned*/ false, SDLoc(Op)).first;
4187 return Op;
4190 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4191 EVT VT = Op.getValueType();
4192 SDLoc dl(Op);
4194 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4196 return Op;
4197 return DAG.UnrollVectorOp(Op.getNode());
4200 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
4203 return DAG.UnrollVectorOp(Op.getNode());
4207 switch (Op.getOpcode()) {
4219 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4220 return DAG.getNode(Opc, dl, VT, Op);
4223 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4224 EVT VT = Op.getValueType();
4226 return LowerVectorINT_TO_FP(Op, DAG);
4227 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4229 if (Op.getOpcode() == ISD::SINT_TO_FP)
4230 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4231 Op.getValueType());
4233 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4234 Op.getValueType());
4235 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4236 /*isSigned*/ false, SDLoc(Op)).first;
4239 return Op;
4242 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4244 SDValue Tmp0 = Op.getOperand(0);
4245 SDValue Tmp1 = Op.getOperand(1);
4246 SDLoc dl(Op);
4247 EVT VT = Op.getValueType();
4324 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4329 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4332 EVT VT = Op.getValueType();
4333 SDLoc dl(Op);
4334 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4336 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4348 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4355 EVT VT = Op.getValueType();
4356 SDLoc dl(Op); // FIXME probably not meaningful
4357 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4402 /// register bank and the source of bitcast, \p Op, operates on the same bank,
4409 SDValue Op = BC->getOperand(0);
4418 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4419 !Op.hasOneUse())
4425 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
4440 SDLoc dl(Op);
4441 SDValue ExtractSrc = Op.getOperand(0);
4458 SDValue Op = N->getOperand(0);
4462 EVT SrcVT = Op.getValueType();
4474 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4476 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4489 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4492 DAG.getVTList(MVT::i32, MVT::i32), Op);
4517 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4519 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4520 EVT VT = Op.getValueType();
4522 SDLoc dl(Op);
4523 SDValue ShOpLo = Op.getOperand(0);
4524 SDValue ShOpHi = Op.getOperand(1);
4525 SDValue ShAmt = Op.getOperand(2);
4527 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4529 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4553 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4555 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4556 EVT VT = Op.getValueType();
4558 SDLoc dl(Op);
4559 SDValue ShOpLo = Op.getOperand(0);
4560 SDValue ShOpHi = Op.getOperand(1);
4561 SDValue ShAmt = Op.getOperand(2);
4564 assert(Op.getOpcode() == ISD::SHL_PARTS);
4585 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4591 SDLoc dl(Op);
4858 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4870 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4876 SDValue Op0 = Op.getOperand(0);
4877 SDValue Op1 = Op.getOperand(1);
4878 SDValue CC = Op.getOperand(2);
4880 EVT VT = Op.getValueType();
4882 SDLoc dl(Op);
5010 static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
5011 SDValue LHS = Op.getOperand(0);
5012 SDValue RHS = Op.getOperand(1);
5013 SDValue Carry = Op.getOperand(2);
5014 SDValue Cond = Op.getOperand(3);
5015 SDLoc DL(Op);
5030 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5055 // Any 1-byte value is OK. Op=0, Cmode=1110.
5066 // Value = 0x00nn: Op=x, Cmode=100x.
5072 // Value = 0xnn00: Op=x, Cmode=101x.
5086 // Value = 0x000000nn: Op=x, Cmode=000x.
5092 // Value = 0x0000nn00: Op=x, Cmode=001x.
5098 // Value = 0x00nn0000: Op=x, Cmode=010x.
5104 // Value = 0xnn000000: Op=x, Cmode=011x.
5115 // Value = 0x0000nnff: Op=x, Cmode=1100.
5123 // Value = 0x00nnffff: Op=x, Cmode=1101.
5159 // Op=1, Cmode=1110.
5173 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5178 bool IsDouble = Op.getValueType() == MVT::f64;
5179 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5194 return Op;
5199 SDLoc DL(Op);
5222 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
5225 SDLoc DL(Op);
5239 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
5242 SDLoc DL(Op);
5647 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5649 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5650 SDLoc dl(Op);
5651 EVT VT = Op.getValueType();
5709 SDValue V = Op.getOperand(i);
5776 if (Op.getOperand(I) == Value)
5780 Ops.push_back(Op.getOperand(I));
5791 Op.getOperand(i)));
5813 SDValue shuffle = ReconstructShuffle(Op, DAG);
5828 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5842 SDValue V = Op.getOperand(i);
5856 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5858 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5859 SDLoc dl(Op);
5860 EVT VT = Op.getValueType();
5888 SDValue V = Op.getOperand(i);
6015 SDValue Entry = Op.getOperand(i);
6177 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
6181 SDValue V1 = Op.getOperand(0);
6182 SDValue V2 = Op.getOperand(1);
6183 SDLoc DL(Op);
6198 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
6200 SDLoc DL(Op);
6201 SDValue OpLHS = Op.getOperand(0);
6215 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
6216 SDValue V1 = Op.getOperand(0);
6217 SDValue V2 = Op.getOperand(1);
6218 SDLoc dl(Op);
6219 EVT VT = Op.getValueType();
6220 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
6379 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
6382 if (SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG))
6388 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6390 SDValue Lane = Op.getOperand(2);
6394 return Op;
6397 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6399 SDValue Lane = Op.getOperand(1);
6403 SDValue Vec = Op.getOperand(0);
6404 if (Op.getValueType() == MVT::i32 &&
6406 SDLoc dl(Op);
6410 return Op;
6413 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6416 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
6418 SDLoc dl(Op);
6420 SDValue Op0 = Op.getOperand(0);
6421 SDValue Op1 = Op.getOperand(1);
6430 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
6635 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6638 EVT VT = Op.getValueType();
6641 SDNode *N0 = Op.getOperand(0).getNode();
6642 SDNode *N1 = Op.getOperand(1).getNode();
6676 return Op;
6681 SDLoc DL(Op);
6780 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6781 EVT VT = Op.getValueType();
6785 SDLoc dl(Op);
6786 SDValue N0 = Op.getOperand(0);
6787 SDValue N1 = Op.getOperand(1);
6815 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6817 EVT VT = Op.getValueType();
6821 SDLoc dl(Op);
6822 SDValue N0 = Op.getOperand(0);
6823 SDValue N1 = Op.getOperand(1);
6891 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6892 EVT VT = Op.getNode()->getValueType(0);
6897 switch (Op.getOpcode()) {
6906 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6907 Op.getOperand(1));
6908 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6909 Op.getOperand(1), Op.getOperand(2));
6912 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6917 SDLoc dl(Op);
6918 SDValue Arg = Op.getOperand(0);
6988 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
6991 EVT VT = Op.getValueType();
6994 SDLoc dl(Op);
7011 Arg.Node = Op.getOperand(AI);
7025 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
7027 assert(Op.getValueType() == MVT::i32 &&
7029 SDLoc dl(Op);
7032 DAG.getEntryNode(), Op.getOperand(1));
7034 return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
7038 SDValue Op, SelectionDAG &DAG, bool Signed,
7043 assert(Op.getValueType() == MVT::i64 &&
7045 SDLoc dl(Op);
7047 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(1),
7049 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(1),
7056 SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
7067 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
7068 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering()))
7074 return Op;
7140 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7141 switch (Op.getOpcode()) {
7143 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
7144 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7145 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7150 return LowerGlobalAddressWindows(Op, DAG);
7152 return LowerGlobalAddressELF(Op, DAG);
7154 return LowerGlobalAddressDarwin(Op, DAG);
7156 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7157 case ISD::SELECT: return LowerSELECT(Op, DAG);
7158 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7159 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
7160 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
7161 case ISD::VASTART: return LowerVASTART(Op, DAG);
7162 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
7163 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
7165 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7167 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
7168 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7169 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7170 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7171 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
7172 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
7173 case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
7174 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
7176 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
7179 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
7180 case ISD::SREM: return LowerREM(Op.getNode(), DAG);
7181 case ISD::UREM: return LowerREM(Op.getNode(), DAG);
7182 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
7184 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
7186 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
7187 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
7188 case ISD::SETCC: return LowerVSETCC(Op, DAG);
7189 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
7190 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
7191 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
7192 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7193 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7194 Op, DAG);
7195 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
7196 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7197 case ISD::MUL: return LowerMUL(Op, DAG);
7200 return LowerDIV_Windows(Op, DAG, /* Signed */ true);
7201 return LowerSDIV(Op, DAG);
7204 return LowerDIV_Windows(Op, DAG, /* Signed */ false);
7205 return LowerUDIV(Op, DAG);
7209 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
7214 return LowerXALUO(Op, DAG);
7216 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
7217 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
7219 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
7222 return LowerDYNAMIC_STACKALLOC(Op, DAG);
7224 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
7225 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
7985 // Expand the pseudo op to a loop.
10193 SDValue Op = N->getOperand(0);
10202 while (Op.getOpcode() == ISD::BITCAST)
10203 Op = Op.getOperand(0);
10204 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
10208 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
10210 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10218 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
10395 SDValue Op = N->getOperand(0);
10396 if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
10397 Op.getOpcode() != ISD::FMUL)
10400 SDValue ConstVec = Op->getOperand(1);
10404 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
10408 unsigned NumLanes = Op.getValueType().getVectorNumElements();
10429 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0),
10452 SDValue Op = N->getOperand(0);
10453 unsigned OpOpcode = Op.getNode()->getOpcode();
10464 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
10466 unsigned NumLanes = Op.getValueType().getVectorNumElements();
10483 SDValue ConvInput = Op.getOperand(0);
10492 Op.getValueType(),
10500 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
10502 while (Op.getOpcode() == ISD::BITCAST)
10503 Op = Op.getOperand(0);
10504 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
10520 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
10523 if (! getVShiftImm(Op, ElementBits, Cnt))
10534 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
10538 if (! getVShiftImm(Op, ElementBits, Cnt))
10785 static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
10787 if (Op.getOpcode() == ARMISD::BFI) {
10790 computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
10794 ConstantSDNode *CI = cast<ConstantSDNode>(Op.getOperand(2));
10800 if (Op.getOpcode() == ARMISD::CMOV) {
10803 computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
10804 computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
10810 return DAG.computeKnownBits(Op, KnownZero, KnownOne);
11580 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
11604 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
11607 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
11615 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
11628 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
11635 switch (Op.getOpcode()) {
11642 if (Op.getResNo() == 0)
11648 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
11652 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
11658 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
11664 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
11842 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11857 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
11996 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
12004 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12046 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
12050 unsigned Opcode = Op->getOpcode();
12054 EVT VT = Op->getValueType(0);
12057 RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(),
12061 TargetLowering::ArgListTy Args = getDivRemArgList(Op.getNode(),
12069 SDLoc dl(Op);
12121 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
12123 SDLoc DL(Op);
12126 SDValue Chain = Op.getOperand(0);
12127 SDValue Size = Op.getOperand(1);
12146 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
12147 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
12151 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
12153 SDValue SrcVal = Op.getOperand(0);
12154 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
12155 SDLoc(Op)).first;
12158 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
12159 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
12164 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
12166 SDValue SrcVal = Op.getOperand(0);
12167 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
12168 SDLoc(Op)).first;
