Lines Matching full:bits
18 class Format<bits<6> val> {
19 bits<6> Value = val;
90 class AddrMode<bits<5> val> {
91 bits<5> Value = val;
112 class IndexMode<bits<2> val> {
113 bits<2> Value = val;
121 class Domain<bits<3> val> {
122 bits<3> Value = val;
296 bits<2> IndexModeBits = IM.Value;
298 bits<6> Form = F.Value;
324 field bits<32> Inst;
325 // Mask of bits that cause an encoding to be UNPREDICTABLE.
329 field bits<32> Unpredictable = 0;
332 field bits<32> SoftFail = Unpredictable;
341 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
433 bits<4> p;
464 bits<4> p; // Predicate operand
465 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
510 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
516 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
529 class AIldr_ex_or_acq<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
533 bits<4> Rt;
534 bits<4> addr;
544 class AIstr_ex_or_rel<bits<2> opcod, bits<2> opcod2, dag oops, dag iops, InstrItinClass itin,
548 bits<4> Rt;
549 bits<4> addr;
560 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
564 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
567 bits<4> Rd;
573 class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
578 class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
582 bits<4> Rd;
588 bits<4> Rt;
589 bits<4> Rt2;
590 bits<4> addr;
603 class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
608 class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
616 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
623 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
630 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
641 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
659 bits<4> Rt;
675 bits<14> offset;
676 bits<4> Rn;
693 bits<14> offset;
694 bits<4> Rn;
714 bits<18> addr;
722 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
726 bits<14> addr;
727 bits<4> Rt;
743 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
748 bits<4> Rt;
759 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
768 bits<4> addr;
769 bits<4> Rt;
780 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
784 bits<14> addr;
785 bits<4> Rt;
804 bits<4> p;
805 bits<16> regs;
806 bits<4> Rn;
815 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
823 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
832 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
836 bits<4> Rd;
837 bits<4> Rn;
838 bits<4> Rm;
847 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
850 bits<4> Ra;
855 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
859 bits<4> Rn;
860 bits<4> Rm;
869 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
872 bits<4> Rd;
877 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
880 bits<4> Ra;
884 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
887 bits<4> RdLo;
888 bits<4> RdHi;
894 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
899 bits<4> Rd;
900 bits<4> Rm;
911 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
915 bits<4> Rd;
916 bits<4> Rm;
926 class ADivA1I<bits<3> opcod, dag oops, dag iops,
930 bits<4> Rd;
931 bits<4> Rn;
932 bits<4> Rm;
960 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
964 bits<4> Rd;
965 bits<4> Rn;
966 bits<4> Rm;
967 bits<5> sh;
1027 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
1121 class T1Encoding<bits<6> opcode> : Encoding16 {
1126 class T1General<bits<5> opcode> : Encoding16 {
1132 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1138 class T1Special<bits<4> opcode> : Encoding16 {
1144 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1148 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1150 class T1BranchCond<bits<4> opcode> : Encoding16 {
1155 // following bits are used for "opA" (see A6.2.4):
1160 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1165 bits<3> Rt;
1166 bits<8> addr;
1171 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1176 bits<3> Rt;
1177 bits<8> addr;
1184 class T1Misc<bits<7> opcode> : Encoding16 {
1212 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1267 bits<4> Rt;
1268 bits<4> Rt2;
1269 bits<13> addr;
1286 bits<4> Rt;
1287 bits<4> Rt2;
1288 bits<4> addr;
1289 bits<9> imm;
1314 class T2Cop<bits<4> opc, dag oops, dag iops, string opcstr, string asm,
1326 class T2Ipreldst<bit signed, bits<2> opcod, bit load, bit pre,
1338 bits<4> Rt;
1339 bits<13> addr;
1359 class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre,
1371 bits<4> Rt;
1372 bits<4> Rn;
1373 bits<9> offset;
1418 bits<4> p;
1434 bits<4> p;
1453 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1459 bits<5> Dd;
1460 bits<13> addr;
1478 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1484 bits<5> Sd;
1485 bits<13> addr;
1503 class AHI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1511 bits<5> Sd;
1512 bits<13> addr;
1548 bits<4> Rn;
1549 bits<13> regs;
1568 bits<4> Rn;
1569 bits<13> regs;
1589 bits<4> Rn;
1590 bits<13> regs;
1604 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1609 bits<5> Dd;
1610 bits<5> Dm;
1630 class ADuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1635 bits<5> Dd;
1636 bits<5> Dm;
1656 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1661 bits<5> Dd;
1662 bits<5> Dn;
1663 bits<5> Dm;
1684 class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1690 bits<5> Dd;
1691 bits<5> Dn;
1692 bits<5> Dm;
1715 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1720 bits<5> Sd;
1721 bits<5> Sm;
1739 class ASuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1745 bits<5> Sd;
1746 bits<5> Sm;
1767 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1776 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1780 bits<5> Sd;
1781 bits<5> Sn;
1782 bits<5> Sm;
1801 class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1807 bits<5> Sd;
1808 bits<5> Sn;
1809 bits<5> Sm;
1831 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1838 bits<5> Sd;
1839 bits<5> Sn;
1840 bits<5> Sm;
1852 class AHuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1859 bits<5> Sd;
1860 bits<5> Sm;
1877 class AHuInp<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1885 bits<5> Sd;
1886 bits<5> Sm;
1905 class AHbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1911 bits<5> Sd;
1912 bits<5> Sn;
1913 bits<5> Sm;
1931 class AHbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1938 bits<5> Sd;
1939 bits<5> Sn;
1940 bits<5> Sm;
1960 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1973 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1977 bits<5> fbits;
1985 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1993 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
2002 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2006 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2010 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2014 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
2064 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
2078 bits<5> Vd;
2079 bits<6> Rn;
2080 bits<4> Rm;
2088 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
2093 bits<3> lane;
2133 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
2148 bits<5> Vd;
2149 bits<13> SIMM;
2160 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2161 bits<5> op11_7, bit op6, bit op4,
2174 bits<5> Vd;
2175 bits<5> Vm;
2184 class N2Vnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
2189 bits<5> Vd;
2190 bits<5> Vm;
2198 // Encode constant bits
2213 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
2214 bits<5> op11_7, bit op6, bit op4,
2227 bits<5> Vd;
2228 bits<5> Vm;
2237 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2249 bits<5> Vd;
2250 bits<5> Vm;
2251 bits<6> SIMM;
2262 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2275 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
2281 bits<5> Vd;
2282 bits<5> Vn;
2283 bits<5> Vm;
2293 class N3Vnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2298 bits<5> Vd;
2299 bits<5> Vn;
2300 bits<5> Vm;
2310 // Encode constant bits
2318 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2326 bits<5> Vd;
2327 bits<5> Vn;
2328 bits<5> Vm;
2339 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2347 bits<5> Vd;
2348 bits<5> Vn;
2349 bits<5> Vm;
2350 bits<2> lane;
2362 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
2375 bits<5> Vd;
2376 bits<5> Vn;
2377 bits<5> Vm;
2388 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2409 bits<5> V;
2410 bits<4> R;
2411 bits<4> p;
2412 bits<4> lane;
2419 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2424 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2429 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
2436 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
2447 bits<5> Vd;
2448 bits<5> Vm;
