Home | History | Annotate | Download | only in ARM

Lines Matching refs:getDeadRegState

1560       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1623         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1624         .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill));