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Lines Matching refs:getDefRegState

768     MIB.addReg(Base, getDefRegState(true))
785     MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
1263     .addReg(Base, getDefRegState(true)) // WB base register
1387       .addReg(Base, getDefRegState(true)) // WB base register
1390       .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
1560       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1623         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1624         .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill));