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Lines Matching refs:getKillRegState

707             .addReg(Base, getKillRegState(KillOldBase));
710             .addReg(Base, getKillRegState(KillOldBase))
720           .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
725           .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
729         .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
769        .addReg(Base, getKillRegState(BaseKill));
779     MIB.addReg(Base, getKillRegState(BaseKill));
785     MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
806     MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
807        .addReg(Regs[1].first, getKillRegState(Regs[1].second));
1264     .addReg(Base, getKillRegState(BaseKill))
1388       .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1391                             getKillRegState(MO.isKill())));
1420         .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1425         .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1561       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1566       .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1567       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1621         .addReg(BaseReg, getKillRegState(BaseKill))
1628         .addReg(BaseReg, getKillRegState(BaseKill))
1631                 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
1633                 getKillRegState(OddDeadKill)  | getUndefRegState(OddUndef));