Lines Matching refs:Op
264 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
273 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
277 const MCOperand &MO = MI.getOperand(Op);
307 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
310 const MCOperand &MO = MI.getOperand(Op);
326 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
329 unsigned SoImm = MI.getOperand(Op).getImm();
346 unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
349 unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
352 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
356 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
359 return 64 - MI.getOperand(Op).getImm();
362 Op,
366 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
369 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
372 unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
375 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
378 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
382 unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
385 unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
388 unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
391 unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
395 unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
1509 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1514 const MCOperand &MO = MI.getOperand(Op);
1523 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1532 unsigned Reg = MI.getOperand(Op).getReg();
1541 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1548 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1560 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1563 const MCOperand &Reg = MI.getOperand(Op);
1564 const MCOperand &Imm = MI.getOperand(Op + 1);
1584 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1587 const MCOperand &Reg = MI.getOperand(Op);
1588 const MCOperand &Imm = MI.getOperand(Op + 1);
1611 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1614 const MCOperand &Reg = MI.getOperand(Op);
1615 const MCOperand &Imm = MI.getOperand(Op + 1);
1632 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1635 const MCOperand &MO = MI.getOperand(Op);
1641 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1644 return 8 - MI.getOperand(Op).getImm();
1648 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1651 return 16 - MI.getOperand(Op).getImm();
1655 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1658 return 32 - MI.getOperand(Op).getImm();
1662 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1665 return 64 - MI.getOperand(Op).getImm();
