Lines Matching refs:RegisterRef
215 struct RegisterRef {
216 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
218 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
219 bool operator== (RegisterRef RR) const {
222 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
223 bool operator< (RegisterRef RR) const {
236 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
237 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
257 MachineInstr *getReachingDefForPred(RegisterRef RD,
265 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
272 bool isIntReg(RegisterRef RR, unsigned &BW);
274 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
323 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
334 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
487 std::set<RegisterRef> DefRegs;
517 std::set<RegisterRef> ImpUses;
521 for (RegisterRef R : ImpUses)
582 RegisterRef RS = SO;
742 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
765 RegisterRef RR = Op;
800 RegisterRef RR = Op;
916 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
930 if (!Op.isReg() || RO != RegisterRef(Op))
966 RegisterRef RT(MS);
1011 RegisterRef RR = Op;
1035 RegisterRef RD = MD;
1084 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1098 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1128 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1209 RegisterRef RD = CI->getOperand(0);
1210 RegisterRef RP = CI->getOperand(1);
1232 RegisterRef RS = S1;
1235 Done = coalesceRegisters(RD, RegisterRef(S1));
1238 RegisterRef RS = S2;
1241 Done = coalesceRegisters(RD, RegisterRef(S2));
