Lines Matching refs:RR
382 return Ref.RR;
389 void RefNode::setRegRef(RegisterRef RR) {
392 Ref.RR = RR;
592 // Determine whether RR is covered by the set of references RRs.
593 bool RegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR) const {
594 if (RRs.count(RR))
598 // on subregisters. If RR itself is not present in RRs, but it has a sub-
601 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {
602 if (RR.Sub != 0)
603 return RRs.count({RR.Reg, 0});
607 // If any super-register of RR is present, then RR is covered.
608 unsigned Reg = RR.Sub == 0 ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
616 // Get the list of references aliased to RR.
617 std::vector<RegisterRef> RegisterAliasInfo::getAliasSet(RegisterRef RR) const {
618 // Do not include RR in the alias set. For virtual registers return an
621 if (TargetRegisterInfo::isVirtualRegister(RR.Reg))
623 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
624 unsigned R = RR.Reg;
625 if (RR.Sub)
626 R = TRI.getSubReg(RR.Reg, RR.Sub);
675 // For a given instruction, check if there are any bits of RR that can remain
682 // Check if the definition of RR produces an unspecified value.
878 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) {
881 PUA.Addr->setRegRef(RR);
894 RegisterRef RR, uint16_t Flags) {
897 DA.Addr->setRegRef(RR);
955 RegisterRef RR = { I->first, 0 };
957 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
1030 RegisterRef RR = PDA.Addr->getRegRef();
1034 if (!Defined.insert(RR).second) {
1037 << Print<RegisterRef>(RR, *this) << " in\n " << *MI
1042 DefM[RR].push(DA);
1043 for (auto A : RAI.getAliasSet(RR)) {
1044 assert(A != RR);
1108 RegisterRef RR = RA.Addr->getRegRef();
1110 return RA.Addr->getNextRef(RR, RelatedStmt, true, *this);
1111 return RA.Addr->getNextRef(RR, RelatedPhi, true, *this);
1215 RegisterRef RR = { Op.getReg(), Op.getSubReg() };
1225 DoneDefs.insert(RR);
1234 RegisterRef RR = { Op.getReg(), Op.getSubReg() };
1235 if (!NeedsImplicit && !ImpDefs.count(RR))
1237 if (DoneDefs.count(RR))
1248 DoneDefs.insert(RR);
1255 RegisterRef RR = { Op.getReg(), Op.getSubReg() };
1261 if (Implicit && !TakeImplicit && !ImpUses.count(RR))
1357 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef {
1359 if (I != RR && RAI.covers(I, RR))
1360 RR = I;
1361 return RR;
1383 auto Aliased = [this,&MaxRefs](RegisterRef RR,
1386 if (RAI.alias(RR, MaxRefs[I]))
1415 RegisterRef RR = MaxRefs[ClosureIdx[X]];
1417 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
1424 RegisterRef RR = MaxRefs[ClosureIdx[X]];
1425 NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA);
1496 RegisterRef RR = TA.Addr->getRegRef();
1504 auto AliasQR = [QR,this] (RegisterRef RR) -> bool {
1505 return RAI.alias(QR, RR);
1507 bool PrecUp = RAI.covers(QR, RR);
1544 RegisterRef RR = RA.Addr->getRegRef();
1546 if (Kind == NodeAttrs::Def && Defs.count(RR))
1548 Defs.insert(RR);
1550 auto F = DefM.find(RR);
1606 RegisterRef RR = PUA.Addr->getRegRef();
1607 linkRefUp<UseNode*>(IA, PUA, DefM[RR]);
