Lines Matching refs:TempReg
349 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
380 unsigned TempReg = createResultReg(RC);
381 emitInst(Mips::ADDiu, TempReg)
384 DestReg = TempReg;
610 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
611 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
612 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
616 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
617 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
618 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
630 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
631 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
632 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
636 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
637 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
638 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
650 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
651 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
652 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
656 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
657 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
658 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
1009 unsigned TempReg = createResultReg(RC);
1011 if (!ResultReg || !TempReg)
1014 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1016 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1075 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1079 emitInst(Opc, TempReg).addReg(SrcReg);
1080 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1365 unsigned TempReg[3];
1367 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1368 if (TempReg[i] == 0)
1371 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1372 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1373 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1374 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1380 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1381 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1382 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1386 unsigned TempReg[8];
1388 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1389 if (TempReg[i] == 0)
1393 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1394 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1395 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1396 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1398 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1399 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1401 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1402 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1403 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1588 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1589 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1590 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1723 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1724 if (!TempReg)
1729 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1732 Op0Reg = TempReg;
1847 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1848 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1850 VReg = TempReg;
1857 unsigned TempReg =
1860 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
