Lines Matching defs:Add
308 setOperationAction(ISD::ADD, MVT::i32, Custom);
310 setOperationAction(ISD::ADD, MVT::i64, Custom);
426 setTargetDAGCombine(ISD::ADD);
557 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
638 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
648 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
783 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
788 SDValue Add = N->getOperand(1);
790 if (Add.getOpcode() != ISD::ADD)
793 SDValue Lo = Add.getOperand(1);
802 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
803 Add.getOperand(0));
804 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
857 case ISD::ADD:
917 case ISD::ADD: return lowerADD(Op, DAG);
1677 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1690 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1771 // page and an additional add instruction takes care of the low bits.
1856 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1857 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1879 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1883 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1960 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1973 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1982 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1987 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2254 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2285 // (set tmp, (ldl (add baseptr, 7), undef))
2304 // (set tmp, (lwl (add baseptr, 3), undef))
2315 // (set tmp0, (lwl (add baseptr, 3), undef))
2335 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2353 // (swl val, (add baseptr, 3))
2366 // (sdl val, (add baseptr, 7))
2409 // (add (frameaddr 0), (frame_to_args_offset))
2411 // (add FrameObject, 0)
2419 return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
2577 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2624 // Add argument registers to the end of the list so that they are
2630 // Add a register mask operand representing the call-preserved registers.
3299 // Add the flag if we have it.
3568 /// vector. If it is invalid, don't add anything to Ops.
3759 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3791 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3817 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3855 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3857 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3996 // Next, add the true and fallthrough blocks as its successors.
