Lines Matching defs:CC
130 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1985 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1992 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2020 } else if (ISD::isUnsignedIntSetCC(CC)) {
2036 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2067 } else if (ISD::isUnsignedIntSetCC(CC)) {
2089 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2090 switch (CC) {
2120 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2122 switch (CC) {
2152 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2159 switch (CC) {
2160 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2161 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2162 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2163 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2164 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2165 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2169 switch (CC) {
2170 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2171 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2172 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2173 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2177 switch (CC) {
2205 switch (CC) {
2206 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2207 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2208 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2209 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2213 switch (CC) {
2214 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2215 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2216 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2217 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2221 switch (CC) {
2263 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2275 switch (CC) {
2310 switch (CC) {
2363 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2384 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2385 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2764 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2774 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2780 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2791 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2796 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2800 default: llvm_unreachable("Invalid CC index");
2823 unsigned BROpc = getPredicateForSetCC(CC);
2942 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2943 unsigned PCC = getPredicateForSetCC(CC);
2969 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
3159 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
3187 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3209 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3231 if (CC != ISD::SETEQ)
