Lines Matching refs:Op
78 static MachineOperand earlyUseOperand(MachineOperand Op) {
79 if (Op.isReg())
80 Op.setIsKill(false);
81 return Op;
432 // structure, but VAEND is a no-op.
728 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
735 if (auto *C = dyn_cast<ConstantSDNode>(Op))
737 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
738 Op.getValueType()));
742 if (auto *C = dyn_cast<ConstantSDNode>(Op))
744 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
745 Op.getValueType()));
749 if (auto *C = dyn_cast<ConstantSDNode>(Op))
751 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
752 Op.getValueType()));
756 if (auto *C = dyn_cast<ConstantSDNode>(Op))
758 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
759 Op.getValueType()));
763 if (auto *C = dyn_cast<ConstantSDNode>(Op))
765 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
766 Op.getValueType()));
770 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1288 // Return true if Op is an intrinsic node with chain that returns the CC value
1291 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1293 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1315 // Return true if Op is an intrinsic node without chain that returns the
1318 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1319 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1458 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1461 unsigned NumOps = Op.getNumOperands();
1464 Ops.push_back(Op.getOperand(0));
1466 Ops.push_back(Op.getOperand(I));
1468 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1470 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1471 SDValue OldChain = SDValue(Op.getNode(), 1);
1478 static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op,
1481 unsigned NumOps = Op.getNumOperands();
1485 Ops.push_back(Op.getOperand(I));
1487 if (Op->getNumValues() == 1)
1488 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1489 assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1490 SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1491 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1680 // Return true if Op is either an unextended load, or a load suitable
1682 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1683 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
2148 SDValue Op;
2151 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2154 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2159 return SDValue(Op.getNode(), Op->getNumValues() - 1);
2275 // of v4f32 value Op.
2277 SDValue Op) {
2279 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2280 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2356 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2358 SDValue CmpOp0 = Op.getOperand(0);
2359 SDValue CmpOp1 = Op.getOperand(1);
2360 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2361 SDLoc DL(Op);
2362 EVT VT = Op.getValueType();
2371 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2372 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2373 SDValue CmpOp0 = Op.getOperand(2);
2374 SDValue CmpOp1 = Op.getOperand(3);
2375 SDValue Dest = Op.getOperand(4);
2376 SDLoc DL(Op);
2380 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2381 Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2397 // Return the absolute or negative absolute of Op; IsNegative decides which.
2398 static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
2400 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2402 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2403 DAG.getConstant(0, DL, Op.getValueType()), Op);
2404 return Op;
2407 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2409 SDValue CmpOp0 = Op.getOperand(0);
2410 SDValue CmpOp1 = Op.getOperand(1);
2411 SDValue TrueOp = Op.getOperand(2);
2412 SDValue FalseOp = Op.getOperand(3);
2413 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2414 SDLoc DL(Op);
2446 EVT VT = Op.getValueType();
2460 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2702 SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
2708 SDLoc DL(Op);
2709 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2730 SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
2736 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2739 SDLoc DL(Op);
2740 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2753 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2755 SDLoc DL(Op);
2756 SDValue In = Op.getOperand(0);
2758 EVT ResVT = Op.getValueType();
2798 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2805 SDValue Chain = Op.getOperand(0);
2806 SDValue Addr = Op.getOperand(1);
2807 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2808 SDLoc DL(Op);
2835 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2837 SDValue Chain = Op.getOperand(0);
2838 SDValue DstPtr = Op.getOperand(1);
2839 SDValue SrcPtr = Op.getOperand(2);
2840 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2841 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2842 SDLoc DL(Op);
2851 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2857 SDValue Chain = Op.getOperand(0);
2858 SDValue Size = Op.getOperand(1);
2859 SDValue Align = Op.getOperand(2);
2860 SDLoc DL(Op);
2919 SDValue Op, SelectionDAG &DAG) const {
2920 SDLoc DL(Op);
2925 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2927 EVT VT = Op.getValueType();
2928 SDLoc DL(Op);
2933 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2934 Op.getOperand(1), Ops[1], Ops[0]);
2950 SDValue LL = Op.getOperand(0);
2951 SDValue RL = Op.getOperand(1);
2967 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2969 EVT VT = Op.getValueType();
2970 SDLoc DL(Op);
2975 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2976 Op.getOperand(1), Ops[1], Ops[0]);
2982 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2986 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2988 SDValue Op0 = Op.getOperand(0);
2989 SDValue Op1 = Op.getOperand(1);
2990 EVT VT = Op.getValueType();
2991 SDLoc DL(Op);
3013 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
3015 EVT VT = Op.getValueType();
3016 SDLoc DL(Op);
3024 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3027 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
3031 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
3032 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
3035 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
3050 return Op;
3057 return Op;
3064 return Op;
3081 SDLoc DL(Op);
3087 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
3089 EVT VT = Op.getValueType();
3090 SDLoc DL(Op);
3091 Op = Op.getOperand(0);
3095 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3096 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3101 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
3103 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
3104 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3105 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
3111 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3117 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
3118 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
3124 return Op;
3129 DAG.computeKnownBits(Op, KnownZero, KnownOne);
3140 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
3141 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
3142 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
3144 // Add up per-byte counts in a binary tree. All bits of Op at
3147 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3151 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3156 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3159 return Op;
3162 SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
3164 SDLoc DL(Op);
3166 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
3168 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
3175 Op.getOperand(0)),
3179 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
3180 return DAG.getNode(SystemZISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
3183 // Op is an atomic load. Lower it into a normal volatile load.
3184 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3186 auto *Node = cast<AtomicSDNode>(Op.getNode());
3187 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3192 // Op is an atomic store. Lower it into a normal volatile store followed
3194 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3196 auto *Node = cast<AtomicSDNode>(Op.getNode());
3197 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3200 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
3204 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3206 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3209 auto *Node = cast<AtomicSDNode>(Op.getNode());
3215 return Op;
3277 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3280 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3282 auto *Node = cast<AtomicSDNode>(Op.getNode());
3286 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3309 return Op;
3312 return lowerATOMIC_LOAD_OP(Op
3317 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3319 auto *Node = cast<AtomicSDNode>(Op.getNode());
3325 return Op;
3360 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3364 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3365 SystemZ::R15D, Op.getValueType());
3368 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3374 SDValue Chain = Op.getOperand(0);
3375 SDValue NewSP = Op.getOperand(1);
3377 SDLoc DL(Op);
3394 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3396 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3399 return Op.getOperand(0);
3401 SDLoc DL(Op);
3402 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3404 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3406 Op.getOperand(0),
3408 Op.getOperand(1)
3426 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3429 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3430 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3431 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3433 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3441 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3444 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3445 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3447 if (Op->getNumValues() == 1)
3449 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3450 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), Glued,
3454 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3457 return lowerThreadPointer(SDLoc(Op), DAG);
3460 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3461 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3464 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3465 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3470 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3471 Op.getOperand(1));
3476 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3477 Op.getOperand(1));
3482 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3483 Op.getOperand(1));
3488 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3489 Op.getOperand(1));
3497 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3498 Op.getOperand(1), Op.getOperand(2));
3738 SDValue Op;
3741 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3745 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3747 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3749 return Op;
3806 // Add an extra element to the shuffle, taking it from element Elem of Op.
3807 // A null Op indicates a vector input whose value will be calculated later;
3810 void GeneralShuffle::add(SDValue Op, unsigned Elem) {
3816 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3824 while (Op.getNode()) {
3825 if (Op.getOpcode() == ISD::BITCAST)
3826 Op = Op.getOperand(0);
3827 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3831 getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3839 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3841 } else if (Op.isUndef()) {
3851 if (Ops[OpNo] == Op)
3854 Ops.push_back(Op);
3933 SDValue Op;
3935 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
3937 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
3938 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3942 static bool isScalarToVector(SDValue Op) {
3943 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
3944 if (!Op.getOperand(I).isUndef())
4007 SDValue Op = BVN->getOperand(I);
4008 if (!Op.isUndef()) {
4010 if (Op.getOpcode() == ISD::Constant)
4011 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
4012 else if (Op.getOpcode() == ISD::ConstantFP)
4013 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
4043 SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
4045 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4060 SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
4063 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4085 SDValue Op = BVN->getOperand(I);
4086 if (Op.getOpcode() == ISD::TRUNCATE)
4087 Op = Op.getOperand(0);
4088 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4089 Op.getOperand(1).getOpcode() == ISD::Constant) {
4090 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4091 GS.add(Op.getOperand(0), Elem);
4093 } else if (Op.isUndef()) {
4109 for (auto &Op : GS.Ops) {
4110 if (!Op.getNode()) {
4111 Op = DAG.getBuildVector(VT, SDLoc(BVN), ResidueOps);
4176 // Merging identical replications is a no-op.
4181 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
4183 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4237 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4241 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4242 SDLoc DL(Op);
4243 EVT VT = Op.getValueType();
4251 SDValue Op = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
4253 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4274 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4276 if (Op.getNode())
4277 return Op;
4284 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4285 if (Op.getNode())
4286 return Op;
4298 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4299 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4302 unsigned NumElements = Op.getNumOperands();
4305 Ops[I] = Op.getOperand(I);
4309 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4311 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4312 SDLoc DL(Op);
4313 EVT VT = Op.getValueType();
4317 SDValue Op0 = Op.getOperand(0);
4326 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4336 GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4342 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4344 SDLoc DL(Op);
4347 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4348 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4351 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4354 SDLoc DL(Op);
4355 SDValue Op0 = Op.getOperand(0);
4356 SDValue Op1 = Op.getOperand(1);
4357 SDValue Op2 = Op.getOperand(2);
4358 EVT VT = Op.getValueType();
4370 return Op;
4383 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4386 SDLoc DL(Op);
4387 SDValue Op0 = Op.getOperand(0);
4388 SDValue Op1 = Op.getOperand(1);
4389 EVT VT = Op.getValueType();
4397 return Op;
4409 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4411 SDValue PackedOp = Op.getOperand(0);
4412 EVT OutVT = Op.getValueType();
4425 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4428 SDValue Op0 = Op.getOperand(0);
4429 SDValue Op1 = Op.getOperand(1);
4430 SDLoc DL(Op);
4431 EVT VT = Op.getValueType();
4452 // Since i32 is the smallest legal type, we either need a no-op
4469 // Since i32 is the smallest legal type, we either need a no-op
4479 return Op;
4482 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
4484 switch (Op.getOpcode()) {
4486 return lowerFRAMEADDR(Op, DAG);
4488 return lowerRETURNADDR(Op, DAG);
4490 return lowerBR_CC(Op, DAG);
4492 return lowerSELECT_CC(Op, DAG);
4494 return lowerSETCC(Op, DAG);
4496 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4498 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4500 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4502 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4504 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4506 return lowerBITCAST(Op, DAG);
4508 return lowerVASTART(Op, DAG);
4510 return lowerVACOPY(Op, DAG);
4512 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4514 return lowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
4516 return lowerSMUL_LOHI(Op, DAG);
4518 return lowerUMUL_LOHI(Op, DAG);
4520 return lowerSDIVREM(Op, DAG);
4522 return lowerUDIVREM(Op, DAG);
4524 return lowerOR(Op, DAG);
4526 return lowerCTPOP(Op, DAG);
4528 return lowerATOMIC_FENCE(Op, DAG);
4530 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
4532 return lowerATOMIC_STORE(Op, DAG);
4534 return lowerATOMIC_LOAD(Op, DAG);
4536 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
4538 return lowerATOMIC_LOAD_SUB(Op, DAG);
4540 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
4542 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
4544 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
4546 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
4548 Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
4550 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
4552 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
4554 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
4556 return lowerATOMIC_CMP_SWAP(Op, DAG);
4558 return lowerSTACKSAVE(Op, DAG);
4560 return lowerSTACKRESTORE(Op, DAG);
4562 return lowerPREFETCH(Op, DAG);
4564 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4566 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4568 return lowerBUILD_VECTOR(Op, DAG);
4570 return lowerVECTOR_SHUFFLE(Op, DAG);
4572 return lowerSCALAR_TO_VECTOR(Op, DAG);
4574 return lowerINSERT_VECTOR_ELT(Op, DAG);
4576 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4578 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACK_HIGH);
4580 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACKL_HIGH);
4582 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
4584 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
4586 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
4710 // producing a result of type ResVT. Op is a possibly bitcast version
4715 EVT VecVT, SDValue Op,
4725 unsigned Opcode = Op.getOpcode();
4728 Op = Op.getOperand(0);
4730 canTreatAsByteVector(Op.getValueType())) {
4735 getVPermMask(cast<ShuffleVectorSDNode>(Op), Bytes);
4749 Op = Op.getOperand(unsigned(First) / Bytes.size());
4752 canTreatAsByteVector(Op.getValueType())) {
4755 EVT OpVT = Op.getValueType();
4765 Op = Op.getOperand(End / OpBytesPerElement - 1);
4766 if (!Op.getValueType().isInteger()) {
4767 EVT VT = MVT::getIntegerVT(Op.getValueType().getSizeInBits());
4768 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4769 DCI.AddToWorklist(Op.getNode());
4772 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
4774 DCI.AddToWorklist(Op.getNode());
4775 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
4777 return Op;
4781 canTreatAsByteVector(Op.getValueType()) &&
4782 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
4784 EVT ExtVT = Op.getValueType();
4785 EVT OpVT = Op.getOperand(0).getValueType();
4800 Op = Op.getOperand(0);
4807 if (Op.getValueType() != VecVT) {
4808 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
4809 DCI.AddToWorklist(Op.getNode());
4811 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
4817 // Optimize vector operations in scalar value Op on the basis that Op
4820 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const {
4824 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4826 SDValue Vec = Op.getOperand(0);
4829 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4912 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4913 DCI.AddToWorklist(Op.getNode());
4914 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
5369 // %RotatedNewVal = OP %RotatedOldVal, %Src2
