Lines Matching defs:CC
2392 static bool canGuaranteeTCO(CallingConv::ID CC) {
2393 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2394 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2398 static bool mayTailCallThisCC(CallingConv::ID CC) {
2399 switch (CC) {
2411 return canGuaranteeTCO(CC);
2417 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2418 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
13319 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
13320 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13321 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
14991 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
15051 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15114 SDValue CC = Op.getOperand(2);
15130 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15131 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15137 SDValue CC = Op.getOperand(2);
15143 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15181 SDValue CC = Op.getOperand(2);
15188 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15250 SDValue CC = Op.getOperand(2);
15252 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15369 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15580 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15588 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15589 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
15602 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15608 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
15624 if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15626 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15631 return DAG.getSetCC(dl, VT, Xor, DAG.getConstant(0, dl, MVT::i1), CC);
15636 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
15660 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
15666 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
15727 SDValue CC;
15887 CC = Cond.getOperand(0);
15896 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15934 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
15946 CC = NewSetCC.getOperand(0);
15954 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
15964 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15988 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15996 SDValue Ops[] = { Op2, Op1, CC, Cond };
16537 SDValue CC;
16578 CC = Cond.getOperand(0);
16587 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16646 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
16658 CC = Cond.getOperand(0).getOperand(0);
16660 Chain, Dest, CC, Cmp);
16661 CC = Cond.getOperand(1).getOperand(0);
16677 CC = DAG.getConstant(CCode, dl, MVT::i8);
16691 Chain, Dest, CC, Cmp);
16695 CC = DAG.getConstant(CCode, dl, MVT::i8);
16708 CC = DAG.getConstant(CCode, dl, MVT::i8);
16734 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
16736 Chain, Dest, CC, Cmp);
16737 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
16764 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
16766 Chain, Dest, CC, Cmp);
16767 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
16784 CC = NewSetCC.getOperand(0);
16793 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
16798 Chain, Dest, CC, Cond);
17712 SDValue CC = Op.getOperand(3);
17713 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
17722 Op.getOperand(2), CC, Rnd);
17727 Op.getOperand(2), CC);
17746 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
17754 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
17758 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
17768 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
17774 switch (CC) {
18020 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
18021 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
18029 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
18031 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
18818 CallingConv::ID CC = Func->getCallingConv();
18821 switch (CC) {
23254 X86::CondCode CC = X86::CondCode(MI.getOperand(3).getImm());
23255 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
23266 (NextMIIt->getOperand(3).getImm() == CC ||
23331 unsigned Opc = X86::GetCondBranchFromCond(CC);
26455 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
26458 // Check for x CC y ? x : y.
26461 switch (CC) {
26523 // Check for x CC y ? y : x -- a min/max with reversed arms.
26526 switch (CC) {
26721 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
26722 switch (CC) {
26726 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
26743 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
26750 CC = ISD::getSetCCInverse(CC, true);
26763 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
26774 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
26786 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
26819 SDValue CC = Cond.getOperand(2);
26821 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
26939 /// Note that this is only legal for some op/cc combinations.
26940 static SDValue combineSetCCAtomicArith(SDValue Cmp, X86::CondCode &CC,
26983 if (CC == X86::COND_S && Addend == 1)
26984 CC = X86::COND_LE;
26985 else if (CC == X86::COND_NS && Addend == 1)
26986 CC = X86::COND_G;
26987 else if (CC == X86::COND_G && Addend == -1)
26988 CC = X86::COND_GE;
26989 else if (CC == X86::COND_LE && Addend == -1)
26990 CC = X86::COND_L;
27016 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
27023 if (CC != X86::COND_E && CC != X86::COND_NE)
27033 bool needOppositeCond = (CC == X86::COND_E);
27083 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
27085 CC = X86::GetOppositeBranchCondition(CC);
27121 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
27123 CC = X86::GetOppositeBranchCondition(CC);
27173 /// Optimize an EFLAGS definition used according to the condition code \p CC
27174 /// into a simpler EFLAGS value, potentially returning a new \p CC and replacing
27176 static SDValue combineSetCCEFLAGS(SDValue EFLAGS, X86::CondCode &CC,
27178 if (SDValue R = checkBoolTestSetCCCombine(EFLAGS, CC))
27180 return combineSetCCAtomicArith(EFLAGS, CC, DAG);
27195 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
27198 if (CC == X86::COND_E || CC == X86::COND_NE) {
27205 return (CC == X86::COND_E) ? FalseOp : TrueOp;
27211 if (SDValue Flags = combineSetCCEFLAGS(Cond, CC, DAG)) {
27212 if (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC)) {
27213 SDValue Ops[] = {FalseOp, TrueOp, DAG.getConstant(CC, DL, MVT::i8),
27227 CC = X86::GetOppositeBranchCondition(CC);
27237 DAG.getConstant(CC, DL, MVT::i8), Cond);
27254 DAG.getConstant(CC, DL, MVT::i8), Cond);
27292 DAG.getConstant(CC, DL, MVT::i8), Cond);
27336 if (CC == X86::COND_NE &&
27338 CC = X86::GetOppositeBranchCondition(CC);
27342 if (CC == X86::COND_E &&
27345 DAG.getConstant(CC, DL, MVT::i8), Cond };
27368 if (CC == X86::COND_NE) {
30290 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
30296 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
30301 DAG.getConstant(0, DL, addV.getValueType()), CC);
30303 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
30308 DAG.getConstant(0, DL, addV.getValueType()), CC);
30312 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
30321 CC = ISD::getSetCCSwappedOperands(CC);
30331 if (CC == ISD::SETGT)
30333 if (CC == ISD::SETLE)
30335 if (CC == ISD::SETEQ || CC == ISD::SETGE)
30338 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
30389 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
30392 if (CC == X86::COND_A) {
30413 if (CC == X86::COND_B)
30417 if (SDValue Flags = combineSetCCEFLAGS(EFLAGS, CC, DAG)) {
30418 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
30431 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
30436 if (SDValue Flags = combineSetCCEFLAGS(EFLAGS, CC, DAG)) {
30437 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
30603 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
30604 if (CC != X86::COND_E && CC != X86::COND_NE)
30618 if (CC == X86::COND_NE)
30678 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
30679 if (CC != ISD::SETGT)
31151 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
