Lines Matching refs:v4f32
635 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
720 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
722 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
723 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
724 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
725 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
726 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
727 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
728 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
880 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
974 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
980 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1026 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32,
1090 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1098 MVT::v4f32, MVT::v2f64 }) {
1380 MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
1827 return MVT::v4f32;
1947 case MVT::v4f32: case MVT::v2f64:
2139 // If we don't have SSE2 available, convert to v4f32 so the generated
2142 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2747 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2818 VecVT = MVT::v4f32;
4402 Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
5363 /// Custom lower build_vector of v4i32 or v4f32.
5453 if (V1.getSimpleValueType() != MVT::v4f32)
5454 V1 = DAG.getBitcast(MVT::v4f32, V1);
5455 if (V2.getSimpleValueType() != MVT::v4f32)
5456 V2 = DAG.getBitcast(MVT::v4f32, V2);
5464 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
6270 if ((!Subtarget.hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
6279 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6393 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget.hasSSE3()) {
6873 // Next, we iteratively mix elements, e.g. for v4f32:
7523 case MVT::v4f32:
8758 V1 = DAG.getUNDEF(MVT::v4f32);
8769 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8770 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8779 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
9202 /// domain crossing penalties, as these are sufficient to implement all v4f32
9208 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
9209 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
9217 DL, MVT::v4f32, V1, V2, Mask, Subtarget, DAG))
9223 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
9225 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
9231 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
9237 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
9247 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
9252 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
9262 DL, MVT::v4f32, V1, V2, Mask, DAG))
9268 return DAG.getNode(X86ISD::MOVLHPS, DL, MVT::v4f32, V1, V2);
9270 return DAG.getNode(X86ISD::MOVHLPS, DL, MVT::v4f32, V2, V1);
9274 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
9278 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
9377 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
9378 DAG.getBitcast(MVT::v4f32, V2), Mask));
10394 case MVT::v4f32:
12659 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12664 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
13592 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
14293 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14339 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
14421 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : (IsF128 ? MVT::f128 : MVT::v4f32);
14475 MVT VecVT = (OpVT == MVT::f32 ? MVT::v4f32 : MVT::v2f64);
14934 else if ((VT == MVT::v4f32 && Subtarget.hasSSE1()) ||
14966 else if ((VT == MVT::v4f32 && Subtarget.hasSSE1()) ||
15769 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
20104 Op = DAG.getBitcast(MVT::v4f32, Op);
21836 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
21844 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
21846 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
21848 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
21901 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
21907 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
24775 ShuffleVT = MVT::v4f32;
24780 ShuffleVT = MVT::v4f32;
24973 ShuffleVT = MVT::v4f32;
24978 ShuffleVT = MVT::v4f32;
24983 ShuffleVT = MVT::v4f32;
24988 ShuffleVT = MVT::v4f32;
25196 (VT == MVT::v2f64 || VT == MVT::v4f32)) {
25208 V1 = DAG.getBitcast(MVT::v4f32, V1);
25210 V2 = DAG.getBitcast(MVT::v4f32, V2);
25212 Res = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
25773 assert(VT == MVT::v4f32 && "INSERTPS ValueType must be MVT::v4f32");
25799 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, Op0, Op1,
25811 assert(VT == MVT::v4f32 && "INSERTPS ValueType must be MVT::v4f32");
25992 if ((!Subtarget.hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
26449 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
27932 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
29562 if (((Subtarget.hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
29851 if (!((Subtarget.hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
31715 case MVT::v4f32:
