Lines Matching refs:Op
272 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
273 // be zero. Op is expected to be a target specific node. Used by DAG
278 const SDValue Op,
287 switch (Op.getOpcode()) {
291 Op.getOperand(1),
297 Op.getOperand(0),
317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const
319 EVT OVT = Op.getValueType();
322 DST = LowerSDIV64(Op, DAG);
324 DST = LowerSDIV32(Op, DAG);
327 DST = LowerSDIV24(Op, DAG);
329 DST = SDValue(Op.getNode(), 0);
335 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const
337 EVT OVT = Op.getValueType();
340 DST = LowerSREM64(Op, DAG);
342 DST = LowerSREM32(Op, DAG);
344 DST = LowerSREM16(Op, DAG);
346 DST = LowerSREM8(Op, DAG);
348 DST = SDValue(Op.getNode(), 0);
354 AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const
356 EVT VT = Op.getValueType();
361 DebugLoc DL = Op.getDebugLoc();
364 VT, Op.getOperand(0));
367 for (unsigned x = 1, y = Op.getNumOperands(); x < y; ++x) {
368 if (Op.getOperand(0) != Op.getOperand(x)) {
377 switch(Op.getNumOperands()) {
382 fourth = Op.getOperand(3);
387 Op.getValueType(),
393 third = Op.getOperand(2);
398 Op.getValueType(),
404 second = Op.getOperand(1);
409 Op.getValueType(),
420 AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
422 SDValue Data = Op.getOperand(0);
423 VTSDNode *BaseType = cast<VTSDNode>(Op.getOperand(1));
424 DebugLoc DL = Op.getDebugLoc();
431 // If the op is less than 32 bits, then it needs to extend to 32bits
444 // Once the sign extension is done, the op needs to be converted to
446 Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType());
474 AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
476 SDValue Chain = Op.getOperand(0);
477 SDValue Cond = Op.getOperand(1);
478 SDValue Jump = Op.getOperand(2);
482 Op.getDebugLoc(),
483 Op.getValueType(),
489 AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const
491 DebugLoc DL = Op.getDebugLoc();
492 EVT OVT = Op.getValueType();
493 SDValue LHS = Op.getOperand(0);
494 SDValue RHS = Op.getOperand(1);
570 AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const
572 DebugLoc DL = Op.getDebugLoc();
573 EVT OVT = Op.getValueType();
574 SDValue LHS = Op.getOperand(0);
575 SDValue RHS = Op.getOperand(1);
637 AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const
639 return SDValue(Op.getNode(), 0);
643 AMDGPUTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const
645 DebugLoc DL = Op.getDebugLoc();
646 EVT OVT = Op.getValueType();
653 SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
654 SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
661 AMDGPUTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const
663 DebugLoc DL = Op.getDebugLoc();
664 EVT OVT = Op.getValueType();
671 SDValue LHS = DAG.getSExtOrTrunc(Op.getOperand(0), DL, INTTY);
672 SDValue RHS = DAG.getSExtOrTrunc(Op.getOperand(1), DL, INTTY);
679 AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const
681 DebugLoc DL = Op.getDebugLoc();
682 EVT OVT = Op.getValueType();
683 SDValue LHS = Op.getOperand(0);
684 SDValue RHS = Op.getOperand(1);
742 AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const
744 return SDValue(Op.getNode(), 0);
