Lines Matching defs:brw
178 /** \see brw.state.depth_region */
191 GLuint brw;
348 * Note that each BRW register contains 256 bits (2 octawords), so when
605 * buffer is involved, and also which brw->state.dirty.cache flag should
624 struct brw_context *brw;
643 void (*emit)( struct brw_context *brw );
646 /* Flags for brw->state.cache.
1094 void brwInitVtbl( struct brw_context *brw );
1112 void brw_prepare_query_begin(struct brw_context *brw);
1113 void brw_emit_query_begin(struct brw_context *brw);
1114 void brw_emit_query_end(struct brw_context *brw);
1125 void brw_validate_textures( struct brw_context *brw );
1140 void brw_upload_urb_fence(struct brw_context *brw);
1144 void brw_upload_cs_urb_state(struct brw_context *brw);
1153 void brw_init_surface_formats(struct brw_context *brw);
1155 brw_update_sol_surface(struct brw_context *brw,
1159 void brw_upload_ubo_surfaces(struct brw_context *brw,
1185 gen6_emit_3dstate_multisample(struct brw_context *brw,
1188 gen6_emit_3dstate_sample_mask(struct brw_context *brw,
1194 gen7_allocate_push_constants(struct brw_context *brw);
1197 gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
1248 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
1251 struct intel_context *intel = &brw->intel;
1260 brw->cache.bo,
1264 return brw->cache.bo->offset + prog_offset;
