Lines Matching refs:rmesa
69 r200ContextPtr rmesa = R200_CONTEXT(ctx);
70 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
75 R200_STATECHANGE( rmesa, ctx );
107 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc;
113 r200ContextPtr rmesa = R200_CONTEXT(ctx);
114 R200_STATECHANGE( rmesa, ctx );
119 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] );
204 r200ContextPtr rmesa = R200_CONTEXT(ctx);
205 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &
215 R200_STATECHANGE( rmesa, ctx );
218 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE;
219 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
220 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
223 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE;
226 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl;
227 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func;
228 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
300 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqnA | funcA;
301 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func;
325 r200ContextPtr rmesa = R200_CONTEXT(ctx);
327 R200_STATECHANGE( rmesa, ctx );
328 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_Z_TEST_MASK;
332 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_NEVER;
335 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_LESS;
338 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_EQUAL;
341 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_LEQUAL;
344 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_GREATER;
347 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_NEQUAL;
350 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_GEQUAL;
353 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_ALWAYS;
360 r200ContextPtr rmesa = R200_CONTEXT(ctx);
361 R200_STATECHANGE( rmesa, ctx );
364 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_WRITE_ENABLE;
366 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_Z_WRITE_ENABLE;
378 r200ContextPtr rmesa = R200_CONTEXT(ctx);
383 c.i = rmesa->hw.fog.cmd[FOG_C];
384 d.i = rmesa->hw.fog.cmd[FOG_D];
390 R200_STATECHANGE(rmesa, tcl);
391 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR;
405 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP;
410 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2;
445 R200_STATECHANGE( rmesa, ctx );
448 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_COLOR_MASK;
449 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= i;
452 GLuint out_0 = rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0];
453 GLuint fog = rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR];
465 if ( fog != rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] ) {
466 R200_STATECHANGE( rmesa, ctx );
467 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = fog;
470 if (out_0 != rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0]) {
471 R200_STATECHANGE( rmesa, vtx );
472 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = out_0;
481 if (c.i != rmesa->hw.fog.cmd[FOG_C] || d.i != rmesa->hw.fog.cmd[FOG_D]) {
482 R200_STATECHANGE( rmesa, fog );
483 rmesa->hw.fog.cmd[FOG_C] = c.i;
484 rmesa->hw.fog.cmd[FOG_D] = d.i;
494 r200ContextPtr rmesa = R200_CONTEXT(ctx);
495 GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
496 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
518 if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
519 R200_STATECHANGE(rmesa, set );
520 rmesa->hw.set.cmd[SET_SE_CNTL] = s;
523 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
524 R200_STATECHANGE(rmesa, tcl );
525 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
531 r200ContextPtr rmesa = R200_CONTEXT(ctx);
534 R200_STATECHANGE( rmesa, set );
535 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_FFACE_CULL_DIR_MASK;
537 R200_STATECHANGE( rmesa, tcl );
538 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_CULL_FRONT_IS_CCW;
543 rmesa->hw.set.cmd[SET_SE_CNTL] |= cull_face;
546 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_CULL_FRONT_IS_CCW;
554 r200ContextPtr rmesa = R200_CONTEXT(ctx);
555 GLfloat *fcmd = (GLfloat *)rmesa->hw.ptp.cmd;
564 R200_STATECHANGE( rmesa, cst );
565 R200_STATECHANGE( rmesa, ptp );
566 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] &= ~0xffff;
567 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] |= ((GLuint)(ctx->Point.Size * 16.0));
575 r200ContextPtr rmesa = R200_CONTEXT(ctx);
576 GLfloat *fcmd = (GLfloat *)rmesa->hw.ptp.cmd;
581 R200_STATECHANGE( rmesa, lin );
582 R200_STATECHANGE( rmesa, ptp );
583 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] &= 0xffff;
584 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] |= (GLuint)(ctx->Point.MinSize * 16.0) << 16;
588 R200_STATECHANGE( rmesa, cst );
589 R200_STATECHANGE( rmesa, ptp );
590 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] &= 0xffff;
591 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] |= (GLuint)(ctx->Point.MaxSize * 16.0) << 16;
595 R200_STATECHANGE( rmesa, vtx );
596 R200_STATECHANGE( rmesa, spr );
597 R200_STATECHANGE( rmesa, ptp );
598 GLfloat *fcmd = (GLfloat *)rmesa->hw.ptp.cmd;
599 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &=
611 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_MULT_ATTENCONST;
613 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_LIN_ATT_ZERO;
616 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_PT_SIZE;
617 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= R200_VTX_POINT_SIZE;
620 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |=
622 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] &= ~R200_OUTPUT_PT_SIZE;
623 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] &= ~R200_VTX_POINT_SIZE;
643 r200ContextPtr rmesa = R200_CONTEXT(ctx);
645 R200_STATECHANGE( rmesa, lin );
646 R200_STATECHANGE( rmesa, set );
651 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] &= ~0xffff;
652 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] |= (GLuint)
656 rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_WIDELINE_ENABLE;
658 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_WIDELINE_ENABLE;
664 r200ContextPtr rmesa = R200_CONTEXT(ctx);
666 R200_STATECHANGE( rmesa, lin );
667 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] =
679 r200ContextPtr rmesa = R200_CONTEXT(ctx);
682 GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE;
684 rrb = radeon_get_colorbuffer(&rmesa->radeon);
697 if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) {
698 R200_STATECHANGE( rmesa, ctx );
699 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag;
702 if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
703 R200_STATECHANGE( rmesa, msk );
704 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = mask;
716 r200ContextPtr rmesa = R200_CONTEXT(ctx);
726 R200_STATECHANGE( rmesa, zbs );
727 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR] = factoru.ui32;
728 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32;
733 r200ContextPtr rmesa = R200_CONTEXT(ctx);
740 if (rmesa->radeon.TclFallback) {
760 r200ContextPtr rmesa = R200_CONTEXT(ctx);
761 uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
763 R200_STATECHANGE( rmesa, tcl );
764 R200_STATECHANGE( rmesa, vtx );
766 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] &= ~(3<<R200_VTX_COLOR_0_SHIFT);
767 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] &= ~(3<<R200_VTX_COLOR_1_SHIFT);
768 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] &= ~R200_OUTPUT_COLOR_0;
769 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] &= ~R200_OUTPUT_COLOR_1;
770 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_LIGHTING_ENABLE;
774 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_DIFFUSE_SPECULAR_COMBINE;
779 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
782 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0;
783 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1;
784 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE;
786 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &=
790 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
792 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0;
793 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE;
795 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
800 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
805 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |=
807 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1;
810 if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
811 R200_STATECHANGE( rmesa, ctx );
812 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
817 if (rmesa->radeon.TclFallback) {
834 r200ContextPtr rmesa = R200_CONTEXT(ctx);
841 if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] &
856 R200_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
870 r200ContextPtr rmesa = R200_CONTEXT(ctx);
877 R200_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
883 r200ContextPtr rmesa = R200_CONTEXT(ctx);
884 GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1];
975 if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1]) {
976 R200_STATECHANGE( rmesa, tcl );
977 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = light_model_ctl1;
985 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1054 R200_DB_STATECHANGE( rmesa, &rmesa->hw.mtl[0] );
1055 R200_DB_STATECHANGE( rmesa, &rmesa->hw.mtl[1] );
1080 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1087 GLuint tmp = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0];
1094 if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0])
1096 R200_STATECHANGE( rmesa, tcl );
1097 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = tmp;
1107 R200_DB_STATECHANGE( rmesa, &rmesa->hw.eye );
1132 R200_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
1141 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1144 GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
1163 R200_STATECHANGE(rmesa, tcl);
1165 rmesa->hw.tcl.cmd[idx] |= flag;
1167 rmesa->hw.tcl.cmd[idx] &= ~flag;
1172 R200_STATECHANGE(rmesa, lit[p]);
1180 R200_STATECHANGE(rmesa, lit[p]);
1183 R200_STATECHANGE(rmesa, tcl);
1185 rmesa->hw.tcl.cmd[idx] |= flag;
1187 rmesa->hw.tcl.cmd[idx] &= ~flag;
1193 R200_STATECHANGE(rmesa, lit[p]);
1201 R200_STATECHANGE(rmesa, lit[p]);
1205 R200_STATECHANGE(rmesa, lit[p]);
1241 R200_DB_STATECHANGE( rmesa, &rmesa->hw.tcl );
1260 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1261 R200_STATECHANGE( rmesa, tcl );
1264 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LOCAL_VIEWER;
1266 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_LOCAL_VIEWER;
1272 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1284 R200_STATECHANGE( rmesa, tcl );
1286 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHT_TWOSIDE;
1288 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~(R200_LIGHT_TWOSIDE);
1289 if (rmesa->radeon.TclFallback) {
1306 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1307 GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
1334 if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
1335 R200_STATECHANGE( rmesa, set );
1336 rmesa->hw.set.cmd[SET_SE_CNTL] = s;
1348 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1351 R200_STATECHANGE( rmesa, ucp[p] );
1352 rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
1353 rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
1354 rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
1355 rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
1360 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1367 R200_STATECHANGE( rmesa, ucp[p] );
1368 rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
1369 rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
1370 rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
1371 rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
1385 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1389 R200_STATECHANGE( rmesa, ctx );
1390 R200_STATECHANGE( rmesa, msk );
1392 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_STENCIL_TEST_MASK;
1393 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~(R200_STENCIL_REF_MASK|
1398 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_NEVER;
1401 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_LESS;
1404 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_EQUAL;
1407 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_LEQUAL;
1410 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_GREATER;
1413 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_NEQUAL;
1416 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_GEQUAL;
1419 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_ALWAYS;
1423 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |= refmask;
1429 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1431 R200_STATECHANGE( rmesa, msk );
1432 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~R200_STENCIL_WRITE_MASK;
1433 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |=
1441 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1443 R200_STATECHANGE( rmesa, ctx );
1444 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(R200_STENCIL_FAIL_MASK |
1450 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_KEEP;
1453 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_ZERO;
1456 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_REPLACE;
1459 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_INC;
1462 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_DEC;
1465 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_INC_WRAP;
1468 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_DEC_WRAP;
1471 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_INVERT;
1477 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_KEEP;
1480 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_ZERO;
1483 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_REPLACE;
1486 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_INC;
1489 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_DEC;
1492 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_INC_WRAP;
1495 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_DEC_WRAP;
1498 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_INVERT;
1504 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_KEEP;
1507 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_ZERO;
1510 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_REPLACE;
1513 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_INC;
1516 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_DEC;
1519 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_INC_WRAP;
1522 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_DEC_WRAP;
1525 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_INVERT;
1541 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1542 __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
1565 R200_STATECHANGE( rmesa, vpt );
1567 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32;
1568 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1569 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32;
1570 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1571 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32;
1572 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32;
1621 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1622 __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
1633 if ( rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] != tx.ui32 ||
1634 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] != ty.ui32 )
1639 R200_STATECHANGE( rmesa, vpt );
1640 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32;
1641 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32;
1646 GLuint m = rmesa->hw.msc.cmd[MSC_RE_MISC];
1659 if ( rmesa->hw.msc.cmd[MSC_RE_MISC] != m ) {
1660 R200_STATECHANGE( rmesa, msc );
1661 rmesa->hw.msc.cmd[MSC_RE_MISC] = m;
1677 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1678 FALLBACK( rmesa, R200_FALLBACK_RENDER_MODE, (mode != GL_RENDER) );
1703 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1708 R200_STATECHANGE( rmesa, msk );
1709 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = r200_rop_tab[rop];
1718 r200ContextPtr rmesa = R200_CONTEXT(ctx);
1735 R200_STATECHANGE( rmesa, ctx );
1737 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ALPHA_TEST_ENABLE;
1739 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ALPHA_TEST_ENABLE;
1755 R200_STATECHANGE( rmesa, tcl );
1757 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (R200_UCP_ENABLE_0<<p);
1761 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(R200_UCP_ENABLE_0<<p);
1775 R200_STATECHANGE(rmesa, ctx );
1777 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_Z_ENABLE;
1779 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_Z_ENABLE;
1784 R200_STATECHANGE(rmesa, ctx );
1786 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
1787 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable;
1789 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_DITHER_ENABLE;
1790 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
1795 R200_STATECHANGE(rmesa, ctx );
1797 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_FOG_ENABLE;
1800 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_FOG_ENABLE;
1801 R200_STATECHANGE(rmesa, tcl);
1802 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
1805 if (rmesa->radeon.TclFallback)
1818 R200_STATECHANGE(rmesa, tcl);
1830 rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] |= flag;
1832 rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag;
1842 rmesa->radeon.NewGLState |= _NEW_TEXTURE;
1846 R200_STATECHANGE( rmesa, ctx );
1848 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_LINE;
1850 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_LINE;
1855 R200_STATECHANGE( rmesa, set );
1857 rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PATTERN_ENABLE;
1859 rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PATTERN_ENABLE;
1864 R200_STATECHANGE( rmesa, tcl );
1866 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_NORMALIZE_NORMALS;
1868 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_NORMALIZE_NORMALS;
1885 R200_STATECHANGE( rmesa, set );
1887 rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_ZBIAS_ENABLE_POINT;
1889 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_ZBIAS_ENABLE_POINT;
1894 R200_STATECHANGE( rmesa, set );
1896 rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_ZBIAS_ENABLE_LINE;
1898 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_ZBIAS_ENABLE_LINE;
1904 R200_STATECHANGE( rmesa, spr );
1908 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |=
1912 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~R200_PS_GEN_TEX_MASK;
1917 R200_STATECHANGE( rmesa, set );
1919 rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_ZBIAS_ENABLE_TRI;
1921 rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_ZBIAS_ENABLE_TRI;
1926 R200_STATECHANGE( rmesa, ctx );
1928 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_POLY;
1930 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_POLY;
1935 R200_STATECHANGE(rmesa, set );
1937 rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_STIPPLE_ENABLE;
1939 rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_STIPPLE_ENABLE;
1945 R200_STATECHANGE( rmesa, tcl );
1947 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_RESCALE_NORMALS;
1949 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_RESCALE_NORMALS;
1955 radeon_firevertices(&rmesa->radeon);
1956 rmesa->radeon.state.scissor.enabled = state;
1970 R200_STATECHANGE( rmesa, ctx );
1972 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE;
1974 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE;
1977 FALLBACK( rmesa, R200_FALLBACK_STENCIL, state );
1988 rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE;
1998 rmesa->curr_vp_hw = NULL;
1999 R200_STATECHANGE( rmesa, vap );
2000 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_PROG_VTX_SHADER_ENABLE;
2006 R200_STATECHANGE( rmesa, mtl[0] );
2007 R200_STATECHANGE( rmesa, mtl[1] );
2008 R200_STATECHANGE( rmesa, fog );
2009 R200_STATECHANGE( rmesa, glt );
2010 R200_STATECHANGE( rmesa, eye );
2012 R200_STATECHANGE( rmesa, mat[i] );
2015 R200_STATECHANGE( rmesa, lit[i] );
2017 R200_STATECHANGE( rmesa, tcl );
2020 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (R200_UCP_ENABLE_0 << i);
2023 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(R200_UCP_ENABLE_0 << i);
2040 R200_STATECHANGE( rmesa, pix[unit] );
2041 R200_STATECHANGE( rmesa, tex[unit] );
2042 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &=
2044 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT;
2047 rmesa->hw.tex[unit].cmd[TEX_PP_TXMULTI_CTL] = 0;
2049 R200_STATECHANGE( rmesa, cst );
2050 R200_STATECHANGE( rmesa, tf );
2051 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
2073 R200_STATECHANGE( rmesa, pix[unit] );
2074 R200_STATECHANGE( rmesa, tex[unit] );
2075 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &=
2077 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT;
2078 rmesa->hw.tex[unit].cmd[TEX_PP_TXMULTI_CTL] = 0;
2080 R200_STATECHANGE( rmesa, cst );
2081 rmesa, tf );
2082 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
2087 R200_STATECHANGE( rmesa, atf );
2088 R200_STATECHANGE( rmesa, afs[1] );
2100 r200ContextPtr rmesa = R200_CONTEXT(ctx);
2105 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]);
2112 R200_STATECHANGE( rmesa, tcl );
2114 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_RESCALE_NORMALS;
2116 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_RESCALE_NORMALS;
2121 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]);
2131 static void upload_matrix( r200ContextPtr rmesa, GLfloat *src, int idx )
2144 R200_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
2147 static void upload_matrix_t( r200ContextPtr rmesa, const GLfloat *src, int idx )
2151 R200_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
2157 r200ContextPtr rmesa = R200_CONTEXT( ctx );
2158 GLuint tpc = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0];
2159 GLuint compsel = rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL];
2164 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]);
2166 rmesa->TexMatEnabled = 0;
2167 rmesa->TexMatCompSel = 0;
2174 rmesa->TexMatEnabled |= (R200_TEXGEN_TEXMAT_0_ENABLE|
2177 rmesa->TexMatCompSel |= R200_OUTPUT_TEX_0 << unit;
2179 if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) {
2183 _math_matrix_mul_matrix( &rmesa->tmpmat,
2185 &rmesa->TexGenMatrix[unit] );
2186 upload_matrix( rmesa, rmesa->tmpmat.m, R200_MTX_TEX0+unit );
2189 upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m,
2193 else if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) {
2194 upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m,
2199 tpc = (rmesa->TexMatEnabled | rmesa->TexGenEnabled);
2200 if (tpc != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]) {
2201 R200_STATECHANGE(rmesa, tcg);
2202 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = tpc;
2206 compsel |= rmesa->TexMatCompSel | rmesa->TexGenCompSel;
2207 if (compsel != rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]) {
2208 R200_STATECHANGE(rmesa, vtx);
2209 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = compsel;
2215 r200ContextPtr rmesa = R200_CONTEXT(ctx);
2222 radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
2224 rrb = radeon_get_colorbuffer(&rmesa->radeon);
2227 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo,
2232 rrb = radeon_get_depthbuffer(&rmesa->radeon);
2235 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo,
2247 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->bo,
2250 radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->mt->bo,
2254 dma_bo = first_elem(&rmesa->radeon.dma.reserved);
2256 ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, dma_bo->bo, RADEON_GEM_DOMAIN_GTT, 0);
2265 r200ContextPtr rmesa = R200_CONTEXT(ctx);
2266 GLuint new_state = rmesa->radeon.NewGLState;
2273 R200_STATECHANGE(rmesa, ctx);
2278 new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */
2291 upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, R200_MTX_MVP );
2296 upload_matrix( rmesa, ctx->ModelviewMatrixStack.Top->m, R200_MTX_MV );
2297 upload_matrix_t( rmesa, ctx->ModelviewMatrixStack.Top->inv, R200_MTX_IMV );
2330 rmesa->radeon.NewGLState = 0;
2367 r200ContextPtr rmesa = R200_CONTEXT(ctx);
2371 fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->radeon.NewGLState);
2375 if (rmesa->radeon.NewGLState)
2377 FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE);
