Lines Matching refs:OPC3
119 #define OPC3(opcode) ((opcode) << 19)
120 #define SET_FLAGS OPC3(0x10)
122 #define ADD (OPC1(0x2) | OPC3(0x00))
123 #define ADDC (OPC1(0x2) | OPC3(0x08))
124 #define AND (OPC1(0x2) | OPC3(0x01))
125 #define ANDN (OPC1(0x2) | OPC3(0x05))
127 #define FABSS (OPC1(0x2) | OPC3(0x34) | DOP(0x09))
128 #define FADDD (OPC1(0x2) | OPC3(0x34) | DOP(0x42))
129 #define FADDS (OPC1(0x2) | OPC3(0x34) | DOP(0x41))
130 #define FCMPD (OPC1(0x2) | OPC3(0x35) | DOP(0x52))
131 #define FCMPS (OPC1(0x2) | OPC3(0x35) | DOP(0x51))
132 #define FDIVD (OPC1(0x2) | OPC3(0x34) | DOP(0x4e))
133 #define FDIVS (OPC1(0x2) | OPC3(0x34) | DOP(0x4d))
134 #define FDTOI (OPC1(0x2) | OPC3(0x34) | DOP(0xd2))
135 #define FDTOS (OPC1(0x2) | OPC3(0x34) | DOP(0xc6))
136 #define FITOD (OPC1(0x2) | OPC3(0x34) | DOP(0xc8))
137 #define FITOS (OPC1(0x2) | OPC3(0x34) | DOP(0xc4))
138 #define FMOVS (OPC1(0x2) | OPC3(0x34) | DOP(0x01))
139 #define FMULD (OPC1(0x2) | OPC3(0x34) | DOP(0x4a))
140 #define FMULS (OPC1(0x2) | OPC3(0x34) | DOP(0x49))
141 #define FNEGS (OPC1(0x2) | OPC3(0x34) | DOP(0x05))
142 #define FSTOD (OPC1(0x2) | OPC3(0x34) | DOP(0xc9))
143 #define FSTOI (OPC1(0x2) | OPC3(0x34) | DOP(0xd1))
144 #define FSUBD (OPC1(0x2) | OPC3(0x34) | DOP(0x46))
145 #define FSUBS (OPC1(0x2) | OPC3(0x34) | DOP(0x45))
146 #define JMPL (OPC1(0x2) | OPC3(0x38))
148 #define OR (OPC1(0x2) | OPC3(0x02))
149 #define ORN (OPC1(0x2) | OPC3(0x06))
150 #define RDY (OPC1(0x2) | OPC3(0x28) | S1A(0))
151 #define RESTORE (OPC1(0x2) | OPC3(0x3d))
152 #define SAVE (OPC1(0x2) | OPC3(0x3c))
154 #define SLL (OPC1(0x2) | OPC3(0x25))
155 #define SLLX (OPC1(0x2) | OPC3(0x25) | (1 << 12))
156 #define SRA (OPC1(0x2) | OPC3(0x27))
157 #define SRAX (OPC1(0x2) | OPC3(0x27) | (1 << 12))
158 #define SRL (OPC1(0x2) | OPC3(0x26))
159 #define SRLX (OPC1(0x2) | OPC3(0x26) | (1 << 12))
160 #define SUB (OPC1(0x2) | OPC3(0x04))
161 #define SUBC (OPC1(0x2) | OPC3(0x0c))
162 #define TA (OPC1(0x2) | OPC3(0x3a) | (8 << 25))
163 #define WRY (OPC1(0x2) | OPC3(0x30) | DA(0))
164 #define XOR (OPC1(0x2) | OPC3(0x03))
165 #define XNOR (OPC1(0x2) | OPC3(0x07))
175 #define SDIV (OPC1(0x2) | OPC3(0x0f))
176 #define SMUL (OPC1(0x2) | OPC3(0x0b))
177 #define UDIV (OPC1(0x2) | OPC3(0x0e))
178 #define UMUL (OPC1(0x2) | OPC3(0x0a))
486 /* u w s */ ARCH_32_64(OPC1(3) | OPC3(0x04) /* stw */, OPC1(3) | OPC3(0x0e) /* stx */),
487 /* u w l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x0b) /* ldx */),
488 /* u b s */ OPC1(3) | OPC3(0x05) /* stb */,
489 /* u b l */ OPC1(3) | OPC3(0x01) /* ldub */,
490 /* u h s */ OPC1(3) | OPC3(0x06) /* sth */,
491 /* u h l */ OPC1(3) | OPC3(0x02) /* lduh */,
492 /* u i s */ OPC1(3) | OPC3(0x04) /* stw */,
493 /* u i l */ OPC1(3) | OPC3(0x00) /* lduw */,
495 /* s w s */ ARCH_32_64(OPC1(3) | OPC3(0x04) /* stw */, OPC1(3) | OPC3(0x0e) /* stx */),
496 /* s w l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x0b) /* ldx */),
497 /* s b s */ OPC1(3) | OPC3(0x05) /* stb */,
498 /* s b l */ OPC1(3) | OPC3(0x09) /* ldsb */,
499 /* s h s */ OPC1(3) | OPC3(0x06) /* sth */,
500 /* s h l */ OPC1(3) | OPC3(0x0a) /* ldsh */,
501 /* s i s */ OPC1(3) | OPC3(0x04) /* stw */,
502 /* s i l */ ARCH_32_64(OPC1(3) | OPC3(0x00) /* lduw */, OPC1(3) | OPC3(0x08) /* ldsw */),
504 /* d s */ OPC1(3) | OPC3(0x27),
505 /* d l */ OPC1(3) | OPC3(0x23),
506 /* s s */ OPC1(3) | OPC3(0x24),
507 /* s l */ OPC1(3) | OPC3(0x20),
