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Lines Matching refs:getDeadRegState

1056       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1110           .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1111           .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill));