Lines Matching full:base
77 outw(RX_DISABLE, BASE + VX_COMMAND);
78 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
80 outw(TX_DISABLE, BASE + VX_COMMAND);
81 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
83 outw(RX_RESET, BASE + VX_COMMAND);
85 outw(TX_RESET, BASE + VX_COMMAND);
87 outw(C_INTR_LATCH, BASE + VX_COMMAND);
88 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
89 outw(SET_INTR_MASK, BASE + VX_COMMAND);
90 outw(SET_RX_FILTER, BASE + VX_COMMAND);
100 /* outw(0, BASE + VX_W0_CONFIG_CTRL); */
103 /* outw(SET_IRQ(0), BASE + VX_W0_RESOURCE_CFG); */
106 /* outw(ENABLE_DRQ_IRQ, BASE + VX_W0_CONFIG_CTRL); */
112 outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i);
114 outw(RX_RESET, BASE + VX_COMMAND);
116 outw(TX_RESET, BASE + VX_COMMAND);
122 inb(BASE + VX_W1_TX_STATUS);
125 S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
127 S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND);
136 outw(ACK_INTR | 0xff, BASE + VX_COMMAND);
139 FIL_BRDCST|FIL_MULTICAST, BASE + VX_COMMAND);
146 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
147 outl(BASE + VX_W3_INTERNAL_CFG, j | (i <<INTERNAL_CONNECTOR_BITS));
149 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
154 outw(RX_ENABLE, BASE + VX_COMMAND);
155 outw(TX_ENABLE, BASE + VX_COMMAND);
196 while(( status=inb(BASE + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
198 outw(TX_RESET, BASE + VX_COMMAND);
199 outw(TX_ENABLE, BASE + VX_COMMAND);
202 outb(0x0, BASE + VX_W1_TX_STATUS);
205 while (inw(BASE + VX_W1_FREE_TX) < len + pad + 4) {
209 outw(len, BASE + VX_W1_TX_PIO_WR_1);
210 outw(0x0, BASE + VX_W1_TX_PIO_WR_1); /* Second dword meaningless */
213 outsw(BASE + VX_W1_TX_PIO_WR_1, d, ETH_ALEN/2);
214 outsw(BASE + VX_W1_TX_PIO_WR_1, nic->node_addr, ETH_ALEN/2);
215 outw(t, BASE + VX_W1_TX_PIO_WR_1);
216 outsw(BASE + VX_W1_TX_PIO_WR_1, p, s / 2);
218 outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1);
221 outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */
224 while((inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0)
238 cst=inw(BASE + VX_STATUS);
247 outw(ACK_INTR | cst, BASE + VX_COMMAND);
248 outw(C_INTR_LATCH, BASE + VX_COMMAND);
253 status = inw(BASE + VX_W1_RX_STATUS);
259 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
273 insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet, rx_fifo / 2);
275 nic->packet[rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1);
279 status = inw(BASE + VX_W1_RX_STATUS);
286 insw(BASE + VX_W1_RX_PIO_RD_1, nic->packet+nic->packetlen, rx_fifo / 2);
288 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1);
304 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
305 while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS);
330 for (i = 0; is_eeprom_busy(BASE) && i < MAX_EEPROMBUSY; i++)
350 outw(EEPROM_CMD_RD | offset, BASE + VX_W0_EEPROM_COMMAND);
353 return (inw(BASE + VX_W0_EEPROM_DATA));
362 vx_connectors = inw(BASE + VX_W3_RESET_OPT) & 0x7f;
377 vx_connector = (inl(BASE + VX_W3_INTERNAL_CFG)
417 j = inl(BASE + VX_W3_INTERNAL_CFG) & ~INTERNAL_CONNECTOR_MASK;
418 outl(j | (i <<INTERNAL_CONNECTOR_BITS), BASE + VX_W3_INTERNAL_CFG);
421 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
424 outw(0, BASE + VX_W4_MEDIA_TYPE);
430 outw(ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE);
433 outw(START_TRANSCEIVER,BASE + VX_COMMAND);
439 outw(LINKBEAT_ENABLE, BASE + VX_W4_MEDIA_TYPE);
451 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
454 outw(0, BASE + VX_W4_MEDIA_TYPE);
486 outw(GLOBAL_RESET, BASE + VX_COMMAND);
506 outw(ntohs(p[i]), BASE + VX_W2_ADDR_0 + (i * 2));
529 PCI_ROM(0x10b7, 0x5952, "3c595-2", "3Com595", 0), /* Vortex 100base-MII */
530 PCI_ROM(0x10b7, 0x9000, "3c900-tpo", "3Com900-TPO", 0), /* 10 Base TPO */
532 PCI_ROM(0x10b7, 0x9004, "3c900b-tpo", "3Com900B-TPO", 0), /* 10 Base TPO */
533 PCI_ROM(0x10b7, 0x9005, "3c900b-combo", "3Com900B-Combo", 0), /* 10 Base Combo */
534 PCI_ROM(0x10b7, 0x9006, "3c900b-tpb2", "3Com900B-2/T", 0), /* 10 Base TP and Base2 */
535 PCI_ROM(0x10b7, 0x900a, "3c900b-fl", "3Com900B-FL", 0), /* 10 Base F */
