Lines Matching full:branch
363 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
368 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \
381 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
386 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \
401 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
410 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \
422 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
428 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \
447 __ Branch(USE_DELAY_SLOT, &done, hs, at, \
453 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
475 __ Branch(USE_DELAY_SLOT, &done, hs, at, \
480 __ Branch(USE_DELAY_SLOT, ool->entry(), eq, at, Operand(zero_reg)); \
544 __ Branch(&done, ne, scratch1,
835 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
841 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
847 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
902 // Branch if the operand is zero
903 __ Branch(&skip_for_zero, eq, i.InputRegister(0), Operand(zero_reg));
911 __ Branch(&end);
1037 // Pseudo-instruction used for tst/branch. No opcode emitted here.
1040 // Pseudo-instruction used for cmp/branch. No opcode emitted here.
1057 // Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
1107 // Psuedo-instruction used for FP cmp/branch. No opcode emitted here.
1245 __ Branch(&done_compare);
1256 __ Branch(&done_compare);
1267 __ Branch(&done_compare);
1278 __ Branch(&done_compare);
1633 void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
1635 Label* tlabel = branch->true_label;
1636 Label* flabel = branch->false_label;
1638 // MIPS does not have condition code flags, so compare and branch are
1640 // emit mips pseudo-instructions, which are handled here by branch
1642 // registers to compare pseudo-op are not modified before this branch op, as
1646 cc = FlagsConditionToConditionTst(branch->condition);
1648 __ Branch(tlabel, cc, at, Operand(zero_reg));
1650 switch (branch->condition) {
1660 UNSUPPORTED_COND(kMipsAddOvf, branch->condition);
1664 switch (branch->condition) {
1674 UNSUPPORTED_COND(kMipsAddOvf, branch->condition);
1678 switch (branch->condition) {
1688 UNSUPPORTED_COND(kMipsMulOvf, branch->condition);
1692 cc = FlagsConditionToConditionCmp(branch->condition);
1693 __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1));
1695 if (!convertCondition(branch->condition, cc)) {
1696 UNSUPPORTED_COND(kMips64CmpS, branch->condition);
1706 if (!convertCondition(branch->condition, cc)) {
1707 UNSUPPORTED_COND(kMips64CmpD, branch->condition);
1721 if (!branch->fallthru) __ Branch(flabel); // no fallthru to flabel.
1726 if (!IsNextInAssemblyOrder(target)) __ Branch(GetLabel(target));
1742 // MIPS does not have condition code flags, so compare and branch are
1785 __ Branch(&tlabel);
1902 __ nop(); // Branch delay slot of the last beq.
1911 __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
2027 __ Branch(&return_label_);
