Lines Matching refs:isU
2970 Bool isU = INSN(23,23) == 1;
2975 binop(isU ? Iop_MullU64 : Iop_MullS64,
2978 isU ? 'u' : 's',
3476 Bool isU = INSN(23,23) == 1;
3490 assign(muld, binop(isU ? Iop_MullU32 : Iop_MullS32,
3495 DIP("%cm%sl %s, %s, %s, %s\n", isU ? 'u' : 's', isAdd ? "add" : "sub",
7486 IRTemp math_ABD ( Bool isU, UInt size, IRExpr* argLE, IRExpr* argRE )
7495 assign(msk, binop(isU ? mkVecCMPGTU(size) : mkVecCMPGTS(size),
7801 widening multiplies are unsigned when isU==True and signed when
7802 isU==False. |size| is the narrow lane size indication. Optionally,
7813 Bool is2, Bool isU, UInt size, HChar mas,
7820 IROp mulOp = isU ? mkVecMULLU(size) : mkVecMULLS(size);
8044 IRTemp math_RHADD ( UInt size, Bool isU, IRTemp aa, IRTemp bb )
8050 IROp opSHR = isU ? mkVecSHRN(size) : mkVecSARN(size);
8451 Bool isU = bitU == 1;
8460 isU, False/*!fromUpperHalf*/, size, mkexpr(src)));
8466 isU, True/*fromUpperHalf*/, size, mkexpr(src)))
8476 DIP("%s %s.%c, %s.%s\n", isU ? "uaddlv" : "saddlv",
8733 Bool isU = (imm4 & 2) == 2;
8741 res = isU ? unop(Iop_8Uto64, lane)
8748 res = isU ? NULL
8755 res = isU ? unop(Iop_16Uto64, lane)
8762 res = isU ? NULL
8769 res = isU ? unop(Iop_32Uto64, lane)
8776 res = isU ? NULL
8783 res = isU ? lane
8791 DIP("%cmov %s, %s.%s[%u]\n", isU ? 'u' : 's',
9185 Bool isU = bitU == 1;
9189 IROp op = isU ? Iop_ShrN64x2 : Iop_SarN64x2;
9193 if (sh == 64 && isU) {
9198 vassert(!isU);
9206 const HChar* nm = isAcc ? (isU ? "usra" : "ssra")
9207 : (isU ? "ushr" : "sshr");
9218 Bool isU = bitU == 1;
9222 IROp op = isU ? Iop_Rsh64Ux2 : Iop_Rsh64Sx2;
9234 const HChar* nm = isAcc ? (isU ? "ursra" : "srsra")
9235 : (isU ? "urshr" : "srshr");
9396 Bool isU = bitU == 1;
9402 IROp opCVT = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32)
9418 DIP("%s %c%u, %c%u, #%u\n", isU ? "ucvtf" : "scvtf",
9434 Bool isU = bitU == 1;
9440 IROp opCVT = isU ? (isD ? Iop_F64toI64U : Iop_F32toI32U)
9457 DIP("%s %c%u, %c%u, #%u\n", isU ? "fcvtzu" : "fcvtzs",
9565 Bool isU = bitU == 1;
9569 qop = isU ? mkVecQADDU(size) : mkVecQADDS(size);
9572 qop = isU ? mkVecQSUBU(size) : mkVecQSUBS(size);
9587 const HChar* nm = isADD ? (isU ? "uqadd" : "sqadd")
9588 : (isU ? "uqsub" : "sqsub");
9634 Bool isU = bitU == 1;
9636 IROp op = isR ? (isU ? mkVecRSHU(size) : mkVecRSHS(size))
9637 : (isU ? mkVecSHU(size) : mkVecSHS(size));
9641 const HChar* nm = isR ? (isU ? "urshl" : "srshl")
9642 : (isU ? "ushl" : "sshl");
9654 Bool isU = bitU == 1;
9656 IROp op = isR ? (isU ? mkVecQANDUQRSH(size) : mkVecQANDSQRSH(size))
9657 : (isU ? mkVecQANDUQSH(size) : mkVecQANDSQSH(size));
9677 const HChar* nm = isR ? (isU ? "uqrshl" : "sqrshl")
9678 : (isU ? "uqshl" : "sqshl");
10107 Bool isU = bitU == 1;
10110 IROp iop = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32)
10119 DIP("%ccvtf %c%u, %c%u\n", isU ? 'u' : 's', c, dd, c, nn);
10378 Bool isU = bitU == 1;
10385 IROp op = isU ? mkVecSHRN(size) : mkVecSARN(size);
10389 if (shift == lanebits && isU) {
10394 vassert(!isU);
10404 const HChar* nm = isAcc ? (isU ? "usra" : "ssra")
10405 : (isU ? "ushr" : "sshr");
10427 Bool isU = bitU == 1;
10434 IROp op = isU ? mkVecRSHU(size) : mkVecRSHS(size);
10447 const HChar* nm = isAcc ? (isU ? "ursra" : "srsra")
10448 : (isU ? "urshr" : "srshr");
10684 Bool isU = bitU == 1;
10704 res = binop(isU ? Iop_ShrN64x2 : Iop_SarN64x2, tmp, mkU8(32-sh));
10713 res = binop(isU ? Iop_ShrN32x4 : Iop_SarN32x4, tmp, mkU8(16-sh));
10722 res = binop(isU ? Iop_ShrN16x8 : Iop_SarN16x8, tmp, mkU8(8-sh));
10731 isU ? 'u' : 's', isQ ? "2" : "",
10751 Bool isU = bitU == 1;
10759 IROp opCVT = isU ? (isD ? Iop_I64UtoF64 : Iop_I32UtoF32)
10779 DIP("%s %s.%s, %s.%s, #%u\n", isU ? "ucvtf" : "scvtf",
10797 Bool isU = bitU == 1;
10805 IROp opCVT = isU ? (isD ? Iop_F64toI64U : Iop_F32toI32U)
10826 DIP("%s %s.%s, %s.%s, #%u\n", isU ? "fcvtzu" : "fcvtzs",
10869 Bool isU = bitU == 1;
10871 IRTemp argL = math_WIDEN_LO_OR_HI_LANES(isU, is2, size, getQReg128(nn));
10872 IRTemp argR = math_WIDEN_LO_OR_HI_LANES(isU, is2, size, getQReg128(mm));
10879 const HChar* nm = isADD ? (isU ? "uaddl" : "saddl")
10880 : (isU ? "usubl" : "ssubl");
10895 Bool isU = bitU == 1;
10897 IRTemp argR = math_WIDEN_LO_OR_HI_LANES(isU, is2, size, getQReg128(mm));
10904 const HChar* nm = isADD ? (isU ? "uaddw" : "saddw")
10905 : (isU ? "usubw" : "ssubw");
10959 Bool isU = bitU == 1;
10961 IRTemp argL = math_WIDEN_LO_OR_HI_LANES(isU, is2, size, getQReg128(nn));
10962 IRTemp argR = math_WIDEN_LO_OR_HI_LANES(isU, is2, size, getQReg128(mm));
10963 IRTemp abd = math_ABD(isU, size+1, mkexpr(argL), mkexpr(argR));
10970 const HChar* nm = isACC ? (isU ? "uabal" : "sabal")
10971 : (isU ? "uabdl" : "sabdl");
10997 Bool isU = bitU == 1;
11005 math_MULL_ACC(&res, is2, isU, size, "mas"[ks],
11011 DIP("%c%s%s %s.%s, %s.%s, %s.%s\n", isU ? 'u' : 's', nm, is2 ? "2" : "",
11110 Bool isU = bitU == 1;
11122 isU, False, size, mkexpr(argL));
11123 argLhi = math_WIDEN_LO_OR_HI_LANES(isU, True, size, mkexpr(argL));
11125 argRlo = math_WIDEN_LO_OR_HI_LANES(isU, False, size, mkexpr(argR));
11126 argRhi = math_WIDEN_LO_OR_HI_LANES(isU, True, size, mkexpr(argR));
11128 IROp opSxR = isU ? mkVecSHRN(size+1) : mkVecSARN(size+1);
11137 const HChar* nm = isADD ? (isU ? "uhadd" : "shadd")
11138 : (isU ? "uhsub" : "shsub");
11149 Bool isU = bitU == 1;
11154 IRTemp res = math_RHADD(size, isU, argL, argR);
11157 DIP("%s %s.%s, %s.%s, %s.%s\n", isU ? "urhadd" : "srhadd",
11169 Bool isU = bitU == 1;
11173 qop = isU ? mkVecQADDU(size) : mkVecQADDS(size);
11176 qop = isU ? mkVecQSUBU(size) : mkVecQSUBS(size);
11191 const HChar* nm = isADD ? (isU ? "uqadd" : "sqadd")
11192 : (isU ? "uqsub" : "sqsub");
11311 Bool isU = bitU == 1;
11313 IROp op = isR ? (isU ? mkVecRSHU(size) : mkVecRSHS(size))
11314 : (isU ? mkVecSHU(size) : mkVecSHS(size));
11318 const HChar* nm = isR ? (isU ? "urshl" : "srshl")
11319 : (isU ? "ushl" : "sshl");
11332 Bool isU = bitU == 1;
11334 IROp op = isR ? (isU ? mkVecQANDUQRSH(size) : mkVecQANDSQRSH(size))
11335 : (isU ? mkVecQANDUQSH(size) : mkVecQANDSQSH(size));
11355 const HChar* nm = isR ? (isU ? "uqrshl" : "sqrshl")
11356 : (isU ? "uqshl" : "sqshl");
11369 Bool isU = bitU == 1;
11371 IROp op = isMAX ? (isU ? mkVecMAXU(size) : mkVecMAXS(size))
11372 : (isU ? mkVecMINU(size) : mkVecMINS(size));
11376 const HChar* nm = isMAX ? (isU ? "umax" : "smax")
11377 : (isU ? "umin" : "smin");
11390 Bool isU = bitU == 1;
11393 IRTemp t1 = math_ABD(isU, size, getQReg128(nn), getQReg128(mm));
11398 const HChar* nm = isACC ? (isU ? "uaba" : "saba")
11399 : (isU ? "uabd" : "sabd");
11490 Bool isU = bitU == 1;
11494 IROp op = isMAX ? (isU ? mkVecMAXU(size) : mkVecMAXS(size))
11495 : (isU ? mkVecMINU(size) : mkVecMINS(size));
11512 const HChar* nm = isMAX ? (isU ? "umaxp" : "smaxp")
11513 : (isU ? "uminp" : "sminp");
11887 Bool isU = bitU == 1;
11896 isU, True/*fromOdd*/, size, mkexpr(src))),
11898 isU, False/*!fromOdd*/, size, mkexpr(src)))));
11904 DIP("%s %s.%s, %s.%s\n", isACC ? (isU ? "uadalp" : "sadalp")
11905 : (isU ? "uaddlp" : "saddlp"),
12424 Bool isU = bitU == 1;
12433 IROp iop = isU ? (isF64 ? Iop_I64UtoF64 : Iop_I32UtoF32)
12445 DIP("%ccvtf %s.%s, %s.%s\n", isU ? 'u' : 's',
12644 Bool isU = bitU == 1;
12667 math_MULL_ACC(&res, is2, isU, size, "mas"[ks],
12675 isU ? 'u' : 's', nm, is2 ? "2" : "",
13412 Bool isU = (op & 1) == 1;
13413 UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0);
13435 isU ? 'u' : 's', nameIRegOrZR(isI64, dd),
13463 Bool isU = (op & 1) == 1;
13464 UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0);
13486 isU ? 'u' : 's', nameQRegLO(dd, isF64 ? Ity_F64 : Ity_F32),
13540 Bool isU = (op & 1) == 1;
13571 UInt ix = (isF64 ? 4 : 0) | (isI64 ? 2 : 0) | (isU ? 1 : 0);
13630 DIP("fcvt%c%c %s, %s\n", ch, isU ? 'u' : 's',
13654 Bool isU = (op & 1) == 1;
13655 UInt ix = (isU ? 4 : 0) | (isI64 ? 2 : 0) | (isF64 ? 1 : 0);
13667 isU ? 'u' : 's', nameQRegLO(dd, isF64 ? Ity_F64 : Ity_F32),
