Lines Matching refs:bitS
187 /*--- Helper bits and pieces for deconstructing the ---*/
274 /*--- Helper bits and pieces for creating IR fragments. ---*/
970 lowbits_to_ignore: 0 = look at all 32 bits
971 8 = look at top 24 bits only
972 16 = look at top 16 bits only
1015 15 of the value. All other bits are ignored. */
1031 bit 7. All other bits are ignored. */
1051 /* Generate IR to get hold of the rounding mode bits in FPSCR, and
1056 /* The ARMvfp encoding for rounding mode bits is:
1066 Which can be done by swapping bits 0 and 1.
1067 The rmode bits are at 23:22 in FPSCR.
1072 we don't zero out bits 24 and above, since the assignment to
1127 bits 7:4, and be zero everywhere else.
1132 /* And 'cond' had better produce a value in which only bits 7:4 are
1141 in 4 bits. Hence we are passing a (COND, OP) pair in the lowest
1142 8 bits of the first argument. */
1173 ARM_CC_OP_ values all fit in 4 bits. Hence we are passing a
1174 (COND, OP) pair in the lowest 8 bits of the first argument. */
1228 /* Build IR to calculate N Z C V in bits 31:28 of the
1588 (bits(N), boolean) UnsignedSatQ( integer i, integer N )
1632 (bits(N), boolean ) SignedSatQ( integer i, integer N )
1722 The C (shco) value computed must be zero in bits 31:1, as the IR
1812 // Lhs of the & limits the shift to 31 bits, so as to
1922 // Lhs of the & limits the shift to 31 bits, so as to
2491 ARM-encoded (N,Z,C,V) group in the lowest 4 bits of an I32 value.
2504 4 bits of 'nzcv'. */
2516 ix fishes the useful bits out of the IR value, bits 6 and 0, and
7947 // memLE(128 bits) == A0 B0 A1 B1
7953 // memLE(128 bits) == A0 B0 A1 B1 A2 B2 A3 B3
7959 // memLE(128 bits) == A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7
7966 // 16 or 8 bits.
7983 // memLE(128 bits) == A0 B0 A1 B1
7989 // memLE(128 bits) == A0 B0 A1 B1 A2 B2 A3 B3
7995 // memLE(128 bits) == A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7
8002 // 16 or 8 bits.
8044 // in the top 16 bits. We now concatentate those four 16-bit
8068 // memLE(192 bits) == A0 B0 C0 A1 B1 C1
8075 // memLE(192 bits) == A0 B0 C0 A1, B1 C1 A2 B2, C2 A3 B3 C3
8100 // 16 or 8 bits.
8123 // memLE(192 bits) == A0 B0 C0 A1 B1 C1
8130 // memLE(192 bits) == A0 B0 C0 A1, B1 C1 A2 B2, C2 A3 B3 C3
8155 // 16 or 8 bits.
8232 // 16 or 8 bits.
8313 // 16 or 8 bits.
8822 The Thumb and ARM encodings are similar for the 24 bottom bits, but
8823 the top 8 bits are slightly different. In both cases, the caller
8824 must pass the entire 32 bits. Callers may pass any instruction;
8847 mode we identify the kind, swizzle the bits around to make it
8905 mode, the caller must pass the entire 32 bits. In ARM mode it must
8906 pass the lower 28 bits. Apart from that, callers may pass any
8914 top 4 bits of the original instruction. For Thumb, the condition
12612 ignore the bottom two bits of the address. However, Cortex-A8
12779 The ARM and Thumb encodings are identical for the low 28 bits of
12781 has the top 4 bits masked out. Caller is responsible for
12782 determining whether the masked-out bits are valid for a CP10/11
12783 insn. The rules for the top 4 bits are:
12798 top 4 bits of the original instruction. For Thumb, the condition
13111 /* When rD is 15, we are copying the top 4 bits of FPSCR
13621 bottom 4 bits of 'nzcv'. */
14132 bottom 4 bits of 'nzcv'. */
14524 need to mask any bits off it. But need to set the lowest bit
14618 // A macro to fish bits out of 'insn'.
14777 UInt bitS = (insn >> 20) & 1; /* 20:20 */
14818 &shop, bitS ? &shco : NULL, dis_buf
14839 if (bitS
14849 if (!bitS)
14852 if (bitS) {
14877 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
14890 &shop, bitS ? &shco : NULL, dis_buf
14897 if (bitS) {
14912 if (bitS) {
14918 nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
14928 if (bitS == 0)
14954 if (bitS == 0)
14992 &shop, bitS ? &shco : NULL, dis_buf
15028 if (!bitS)
15031 if (bitS) {
15051 name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
15279 STR: lowest 2 bits of address are ignored
15280 LDR: if the lowest 2 bits of the address are nonzero
15281 then the loaded value is rotated right by 8 * the lowest 2 bits
15383 do a branch, since they only load 16 bits at most, but we
15711 UInt bitS = (insn >> 20) & 1; /* 20:20 */
15726 if (bitS) {
15734 if (bitS) {
15742 bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
15796 UInt bitS = (insn >> 20) & 1; /* 20:20 */
15802 if (bitS == 1 && isMLS == 1) {
15822 if (bitS) {
15831 if (bitS) {
15839 isMLS ? 's' : 'a', bitS ? 's' : ' ',
15849 UInt bitS = (insn >> 20) & 1; /* 20:20 */
15871 if (bitS) {
15880 if (bitS) {
15888 isS ? 's' : 'u', bitS ? 's' : ' ',
15898 UInt bitS = (insn >> 20) & 1; /* 20:20 */
15924 if (bitS) {
15933 if (bitS) {
15941 isS ? 's' : 'u', bitS ? 's' : ' ', nCC(INSN_COND),
17485 /* A macro to fish bits out of insn0. There's also INSN1, to fish
17486 bits out of insn1, but that's defined only after the end of the
17492 UShort insn0; /* first 16 bits of the insn */
17493 UShort insn1; /* second 16 bits of the insn */
17518 /* Insns could be 2 or 4 bytes long. Just get the first 16 bits at
17521 unlikely, but ..) if the second 16 bits aren't actually
19243 /* second 16 bits of the instruction, if any */
20725 more bits available for the jump offset, so it has a 16-times
