Lines Matching full:binop
1435 switch (e->Iex.Binop.op) {
1453 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1459 e->Iex.Binop.arg2, IEndianess);
1463 e->Iex.Binop.arg2, IEndianess);
1473 switch (e->Iex.Binop.op) {
1486 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1492 ri_srcR = iselWordExpr_RH5u(env, e->Iex.Binop.arg2, IEndianess);
1494 ri_srcR = iselWordExpr_RH6u(env, e->Iex.Binop.arg2, IEndianess);
1529 if (e->Iex.Binop.op == Iop_DivS32 ||
1530 e->Iex.Binop.op == Iop_DivU32 ||
1531 e->Iex.Binop.op == Iop_DivS32E ||
1532 e->Iex.Binop.op == Iop_DivU32E) {
1533 Bool syned = toBool((e->Iex.Binop.op == Iop_DivS32) || (e->Iex.Binop.op == Iop_DivS32E));
1535 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1536 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1538 PPCInstr_Div( ( ( e->Iex.Binop.op == Iop_DivU32E )
1539 || ( e->Iex.Binop.op == Iop_DivS32E ) ) ? True
1548 if (e->Iex.Binop.op == Iop_DivS64 ||
1549 e->Iex.Binop.op == Iop_DivU64 || e->Iex.Binop.op == Iop_DivS64E
1550 || e->Iex.Binop.op == Iop_DivU64E ) {
1551 Bool syned = toBool((e->Iex.Binop.op == Iop_DivS64) ||(e->Iex.Binop.op == Iop_DivS64E));
1553 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1554 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1557 PPCInstr_Div( ( ( e->Iex.Binop.op == Iop_DivS64E )
1558 || ( e->Iex.Binop.op
1570 if (e->Iex.Binop.op == Iop_Mul32
1571 || e->Iex.Binop.op == Iop_Mul64) {
1573 Bool sz32 = (e->Iex.Binop.op != Iop_Mul64);
1575 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1576 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1584 && (e->Iex.Binop.op == Iop_MullU32
1585 || e->Iex.Binop.op == Iop_MullS32)) {
1589 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS32);
1590 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1591 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1606 if (e->Iex.Binop.op == Iop_CmpORD32S
1607 || e->Iex.Binop.op == Iop_CmpORD32U) {
1608 Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD32S);
1610 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1611 PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2,
1621 if (e->Iex.Binop.op == Iop_CmpORD64S
1622 || e->Iex.Binop.op == Iop_CmpORD64U) {
1623 Bool syned = toBool(e->Iex.Binop.op == Iop_CmpORD64S);
1625 HReg srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1626 PPCRH* srcR = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2,
1637 if (e->Iex.Binop.op == Iop_Max32U) {
1638 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1639 HReg r2 = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1649 if (e->Iex.Binop.op == Iop_32HLto64) {
1650 HReg r_Hi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
1651 HReg r_Lo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
1667 if ((e->Iex.Binop.op == Iop_CmpF64) ||
1668 (e->Iex.Binop.op == Iop_CmpD64) ||
1669 (e->Iex.Binop.op == Iop_CmpD128)) {
1681 if (e->Iex.Binop.op == Iop_CmpF64) {
1682 fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
1683 fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
1686 } else if (e->Iex.Binop.op == Iop_CmpD64) {
1687 fr_srcL = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess);
1688 fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
1691 } else { // e->Iex.Binop.op == Iop_CmpD128
1692 iselDfp128Expr(&fr_srcL, &fr_srcL_lo, env, e->Iex.Binop.arg1,
1694 iselDfp128Expr(&fr_srcR, &fr_srcR_lo, env, e->Iex.Binop.arg2,
1747 if ( e->Iex.Binop.op == Iop_F64toI32S ||
1748 e->Iex.Binop.op == Iop_F64toI32U ) {
1752 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
1757 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1761 e->Iex.Binop.op == Iop_F64toI32S ? True/*syned*/
1779 if (e->Iex.Binop.op == Iop_F64toI64S || e->Iex.Binop.op == Iop_F64toI64U ) {
1783 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2,
1789 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1793 ( e->Iex.Binop.op == Iop_F64toI64S ) ? True
1806 if (e->Iex.Binop.op == Iop_D64toI64S ) {
1809 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
1814 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1827 if (e->Iex.Binop.op == Iop_D128toI64S ) {
1835 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
1836 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
2550 && e->Iex.Binop.op == Iop_Add64
2551 && e->Iex.Binop.arg2->tag == Iex_Const
2552 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U64
2553 && (aligned4imm ? uLong_is_4_aligned(e->Iex.Binop.arg2
2556 && uLong_fits_in_16_bits(e->Iex.Binop.arg2
2558 return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U64,
2559 iselWordExpr_R(env, e->Iex.Binop.arg1,
2565 && e->Iex.Binop.op == Iop_Add64) {
2566 Binop.arg1, IEndianess);
2567 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
2577 && e->Iex.Binop.op == Iop_Add32
2578 && e->Iex.Binop.arg2->tag == Iex_Const
2579 && e->Iex.Binop.arg2->Iex.Const.con->tag == Ico_U32
2580 && uInt_fits_in_16_bits(e->Iex.Binop.arg2
2582 return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.U32,
2583 iselWordExpr_R(env, e->Iex.Binop.arg1,
2589 && e->Iex.Binop.op == Iop_Add32) {
2590 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2591 HReg r_idx = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
2899 && (e->Iex.Binop.op == Iop_CmpEQ32
2900 || e->Iex.Binop.op == Iop_CmpNE32
2901 || e->Iex.Binop.op == Iop_CmpLT32S
2902 || e->Iex.Binop.op == Iop_CmpLT32U
2903 || e->Iex.Binop.op == Iop_CmpLE32S
2904 || e->Iex.Binop.op == Iop_CmpLE32U)) {
2905 Bool syned = (e->Iex.Binop.op == Iop_CmpLT32S ||
2906 e->Iex.Binop.op == Iop_CmpLE32S);
2907 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2908 PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, IEndianess);
2912 switch (e->Iex.Binop.op) {
2948 && (e->Iex.Binop.op == Iop_CmpEQ64
2949 || e->Iex.Binop.op == Iop_CmpNE64
2950 || e->Iex.Binop.op == Iop_CmpLT64S
2951 || e->Iex.Binop.op == Iop_CmpLT64U
2952 || e->Iex.Binop.op == Iop_CmpLE64S
2953 || e->Iex.Binop.op == Iop_CmpLE64U)) {
2954 Bool syned = (e->Iex.Binop.op == Iop_CmpLT64S ||
2955 e->Iex.Binop.op == Iop_CmpLE64S);
2956 HReg r1 = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
2957 PPCRH* ri2 = iselWordExpr_RH(env, syned, e->Iex.Binop.arg2, IEndianess);
2962 switch (e->Iex.Binop.op) {
2977 && e->Iex.Binop.op == Iop_CmpNE8
2978 && isZeroU8(e->Iex.Binop.arg2)) {
2979 HReg arg = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3046 switch (e->Iex.Binop.op) {
3052 Bool syned = toBool(e->Iex.Binop.op == Iop_MullS64);
3053 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3054 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3068 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3069 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3131 IROp op_binop = e->Iex.Binop.op;
3134 iselInt64Expr(rHi, rMedHi, env, e->Iex.Binop.arg1, IEndianess);
3135 iselInt64Expr(rMedLo, rLo, env, e->Iex.Binop.arg2, IEndianess);
3138 vex_printf("iselInt128Expr_to_32x4_wrk: Binop case 0x%x not found\n",
3248 IROp op_binop = e->Iex.Binop.op;
3256 HReg r_srcL = iselWordExpr_R(env, e->Iex.Binop.arg1,
3258 HReg r_srcR = iselWordExpr_R(env, e->Iex.Binop.arg2,
3280 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess);
3281 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2, IEndianess);
3294 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1, IEndianess);
3295 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2, IEndianess);
3307 *rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
3308 *rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3318 HReg fsrc = iselDblExpr(env, e->Iex.Binop.arg2,
3324 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3347 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
3351 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3373 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3374 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
3848 if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_I64UtoF32) {
3851 HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
3856 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
3879 iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2, IEndianess);
3882 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4059 switch (e->Iex.Binop.op) {
4065 HReg fr_src = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
4066 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4074 if (e->Iex.Binop.op == Iop_RoundF64toF32) {
4076 HReg r_src = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
4077 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4083 if (e->Iex.Binop.op == Iop_I64StoF64 || e->Iex.Binop.op == Iop_I64UtoF64) {
4086 HReg isrc = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
4091 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4098 e->Iex.Binop.op == Iop_I64StoF64,
4115 iselInt64Expr(&isrcHi, &isrcLo, env, e->Iex.Binop.arg2,
4119 set_FPU_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4127 e->Iex.Binop.op == Iop_I64StoF64,
4268 if (e->Iex.Binop.op == Iop_D64toD32) {
4270 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4271 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4358 HReg fr_srcL = iselDblExpr(env, e->Iex.Binop.arg1, IEndianess);
4359 HReg fr_srcR = iselDblExpr(env, e->Iex.Binop.arg2, IEndianess);
4375 switch (e->Iex.Binop.op) {
4386 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4387 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4394 PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4401 fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4406 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4407 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4415 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4420 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
4427 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg2,
4439 switch (e->Iex.Binop.op) {
4446 HReg fr_src = iselDfp64Expr(env, e->Iex.Binop.arg1, IEndianess);
4447 PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess);
4456 switch (e->Iex.Binop.op) {
4464 HReg fr_srcR = iselDfp64Expr(env, e->Iex.Binop.arg2, IEndianess);
4470 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
4479 iselInt64Expr(&tmpHi, &tmpLo, env, e->Iex.Binop.arg1,
4632 switch (e->Iex.Binop.op) {
4634 r_srcHi = iselDfp64Expr( env, e->Iex.Binop.arg1, IEndianess );
4635 r_srcLo = iselDfp64Expr( env, e->Iex.Binop.arg2, IEndianess );
4644 set_FPU_DFP_rounding_mode( env, e->Iex.Binop.arg1, IEndianess );
4645 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4660 PPCRI* shift = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess);
4663 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg1,
4666 if (e->Iex.Binop.op == Iop_ShrD128)
4679 PPCRI* r_rmc = iselWordExpr_RI(env, e->Iex.Binop.arg1, IEndianess);
4682 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4699 iselDfp128Expr(&r_srcHi, &r_srcLo, env, e->Iex.Binop.arg2,
4704 HReg tmp = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
4725 vex_printf( "ERROR: iselDfp128Expr_wrk, UNKNOWN binop case %d\n",
4726 (Int)e->Iex.Binop.op );
5072 switch (e->Iex.Binop.op) {
5090 iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2, IEndianess);
5094 iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1, IEndianess);
5104 HReg rHi = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess);
5105 HReg rLo = iselWordExpr_R(env, e->Iex.Binop.arg2, IEndianess);
5140 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5141 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5148 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5149 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5173 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5174 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5205 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5206 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5240 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5241 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5278 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5279 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5305 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5306 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5315 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5317 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5326 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5328 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5337 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5339 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5348 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5350 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5359 HReg r_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5360 HReg v_shft = mk_AvDuplicateRI(env, e->Iex.Binop.arg2, IEndianess);
5368 HReg v_src = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5369 HReg v_ctl = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5379 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5380 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
5389 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
5391 PPCRI* s_field = iselWordExpr_RI(env, e->Iex.Binop.arg2, IEndianess);
5397 } /* switch (e->Iex.Binop.op) */
