Lines Matching refs:VIXL_ASSERT
79 VIXL_ASSERT(rm_.IsValid());
87 VIXL_ASSERT(rm_.IsValid());
88 VIXL_ASSERT(shift_.IsRRX());
97 VIXL_ASSERT(rm_.IsValid());
98 VIXL_ASSERT(!shift_.IsRRX());
102 VIXL_ASSERT(amount_ <= 31);
105 VIXL_ASSERT(amount_ <= 31);
109 VIXL_ASSERT(amount_ <= 32);
125 VIXL_ASSERT(rm_.IsValid() && rs_.IsValid());
126 VIXL_ASSERT(!shift_.IsRRX());
143 VIXL_ASSERT(IsInt32(immediate) || IsUint32(immediate));
150 VIXL_ASSERT(IsUint32(address_as_integral));
169 VIXL_ASSERT(IsImmediate());
174 VIXL_ASSERT(IsImmediate());
181 VIXL_ASSERT(IsImmediateShiftedRegister() || IsRegisterShiftedRegister());
186 VIXL_ASSERT(IsImmediateShiftedRegister() || IsRegisterShiftedRegister());
191 VIXL_ASSERT(IsImmediateShiftedRegister());
196 VIXL_ASSERT(IsRegisterShiftedRegister());
287 VIXL_ASSERT(sizeof(T) <= sizeof(uint32_t));
288 VIXL_ASSERT(CanConvert<T>());
296 VIXL_ASSERT(CanConvert<uint64_t>());
302 VIXL_ASSERT(CanConvert<float>());
307 VIXL_ASSERT(CanConvert<double>());
325 VIXL_ASSERT(sizeof(T) < sizeof(uint32_t));
395 VIXL_ASSERT(rm_.IsValid());
404 VIXL_ASSERT(IsRegister());
440 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kSRegister));
482 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kDRegister));
517 VIXL_ASSERT(rm_.IsValid());
521 VIXL_ASSERT(IsRegister() && (rm_.GetType() == CPURegister::kQRegister));
659 VIXL_ASSERT(rn_.IsValid());
676 VIXL_ASSERT(rn_.IsValid());
686 VIXL_ASSERT(rn_.IsValid());
688 VIXL_ASSERT(offset >= 0);
703 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
717 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
737 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
738 VIXL_ASSERT(shift_.IsRRX());
753 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
754 VIXL_ASSERT(shift_.IsRRX());
776 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
797 VIXL_ASSERT(rn_.IsValid() && rm_.IsValid());
862 VIXL_ASSERT(shift_amount_ <= 31);
865 VIXL_ASSERT(shift_amount_ <= 31);
869 VIXL_ASSERT(shift_amount_ <= 32);
893 VIXL_ASSERT(addrmode != PreIndex);
901 VIXL_ASSERT(addrmode != PreIndex);
