Lines Matching full:board
378 #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */
379 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
380 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */
381 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
383 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
386 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
387 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
388 #define BFL_LTECOEX 0x00000200 /* Board has LTE coex capability */
389 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
390 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */
391 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
392 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */
394 /* Board's BTC 2wire is in the alternate gpios OBSLETE */
396 #define BFL_NOPA 0x00010000 /* Board has no PA */
397 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
398 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
399 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
400 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
402 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
410 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
411 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
420 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
422 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
423 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
424 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
425 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
426 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
427 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */
428 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace
431 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
432 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
461 /* board rework */
468 #define BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */
470 #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
471 #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
479 #define BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */
503 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
517 #define BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */
518 #define BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */
519 #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */
