Lines Matching defs:sig
10 // via struct sig, below.
14 // Synchronization between sigsend and signal_recv is based on the sig.state
16 // sigReceiving means that signal_recv is blocked on sig.Note and there are no
18 // sigSending means that sig.mask *may* contain new pending signals,
22 // When signal_recv is unblocked, it resets sig.Note and rechecks sig.mask.
24 // unnecessary rechecks of sig.mask, but it cannot lead to missed signals
36 var sig struct {
56 if !sig.inuse || s >= uint32(32*len(sig.wanted)) || sig.wanted[s/32]&bit == 0 {
62 mask := sig.mask[s/32]
66 if atomic.Cas(&sig.mask[s/32], mask, mask|bit) {
74 switch atomic.Load(&sig.state) {
78 if atomic.Cas(&sig.state, sigIdle, sigSending) {
85 if atomic.Cas(&sig.state, sigReceiving, sigIdle) {
86 notewakeup(&sig.note)
102 if sig.recv[i/32]&(1<<(i&31)) != 0 {
103 sig.recv[i/32] &^= 1 << (i & 31)
111 switch atomic.Load(&sig.state) {
115 if atomic.Cas(&sig.state, sigIdle, sigReceiving) {
116 notetsleepg(&sig.note, -1)
117 noteclear(&sig.note)
121 if atomic.Cas(&sig.state, sigSending, sigIdle) {
128 for i := range sig.mask {
129 sig.recv[i] = atomic.Xchg(&sig.mask[i], 0)
137 if !sig.inuse {
141 sig.inuse = true // enable reception of signals; cannot disable
142 noteclear(&sig.note)
146 if s >= uint32(len(sig.wanted)*32) {
149 sig.wanted[s/32] |= 1 << (s & 31)
150 sig.ignored[s/32] &^= 1 << (s & 31)
157 if s >= uint32(len(sig.wanted)*32) {
160 sig.wanted[s/32] &^= 1 << (s & 31)
167 if s >= uint32(len(sig.wanted)*32) {
170 sig.wanted[s/32] &^= 1 << (s & 31)
171 sig.ignored[s/32] |= 1 << (s & 31)
177 return sig.ignored[s/32]&(1<<(s&31)) != 0
