Lines Matching defs:immed
898 unsigned int immed, temp;
1038 immed = 0;
1043 immed = exp.X_add_number;
1066 inst |= (immed << IMM_LOW) & IMM_MASK;
1075 immed = immed + 4;
1080 inst |= (immed << IMM_LOW) & IMM_MASK;
1085 temp = immed & 0xFFFF8000;
1097 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1106 inst |= (immed << IMM_LOW) & IMM_MASK;
1141 immed = exp.X_add_number;
1144 if (immed != (immed % 32))
1147 immed = immed % 32;
1151 inst |= (immed << IMM_LOW) & IMM5_MASK;
1217 immed); /* Get rfslN. */
1221 immed = 0;
1229 inst |= (immed << IMM_LOW) & RFSL_MASK;
1256 immed = exp.X_add_number;
1259 inst |= (immed << IMM_LOW) & IMM15_MASK;
1271 op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
1275 immed = 0;
1283 inst |= (immed << IMM_LOW) & RFSL_MASK;
1289 op_end = parse_reg (op_end + 1, &immed); /* Get rfslN. */
1293 immed = 0;
1295 inst |= (immed << IMM_LOW) & RFSL_MASK;
1351 immed = opcode->immval_mask | REG_MSR_MASK;
1353 immed = opcode->immval_mask | REG_PC_MASK;
1355 immed = opcode->immval_mask | REG_EAR_MASK;
1357 immed = opcode->immval_mask | REG_ESR_MASK;
1359 immed = opcode->immval_mask | REG_FSR_MASK;
1361 immed = opcode->immval_mask | REG_BTR_MASK;
1363 immed = opcode->immval_mask | REG_EDR_MASK;
1365 immed = opcode->immval_mask | REG_PID_MASK;
1367 immed = opcode->immval_mask | REG_ZPR_MASK;
1369 immed = opcode->immval_mask | REG_TLBX_MASK;
1371 immed = opcode->immval_mask | REG_TLBLO_MASK;
1373 immed = opcode->immval_mask | REG_TLBHI_MASK;
1375 immed = opcode->immval_mask | REG_SHR_MASK;
1377 immed = opcode->immval_mask | REG_SLR_MASK;
1379 immed = opcode->immval_mask | REG_PVR_MASK | reg2;
1383 inst |= (immed << IMM_LOW) & IMM_MASK;
1404 immed = opcode->immval_mask | REG_MSR_MASK;
1406 immed = opcode->immval_mask | REG_PC_MASK;
1408 immed = opcode->immval_mask | REG_EAR_MASK;
1410 immed = opcode->immval_mask | REG_ESR_MASK;
1412 immed = opcode->immval_mask | REG_FSR_MASK;
1414 immed = opcode->immval_mask | REG_BTR_MASK;
1416 immed = opcode->immval_mask | REG_EDR_MASK;
1418 immed = opcode->immval_mask | REG_PID_MASK;
1420 immed = opcode->immval_mask | REG_ZPR_MASK;
1422 immed = opcode->immval_mask | REG_TLBX_MASK;
1424 immed = opcode->immval_mask | REG_TLBLO_MASK;
1426 immed = opcode->immval_mask | REG_TLBHI_MASK;
1428 immed = opcode->immval_mask | REG_TLBSX_MASK;
1430 immed = opcode->immval_mask | REG_SHR_MASK;
1432 immed = opcode->immval_mask | REG_SLR_MASK;
1436 inst |= (immed << IMM_LOW) & IMM_MASK;
1530 immed = 0;
1535 immed = exp.X_add_number;
1538 temp = immed & 0xFFFF8000;
1550 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1559 inst |= (immed << IMM_LOW) & IMM_MASK;
1596 immed = 0;
1601 immed = exp.X_add_number;
1604 temp = immed & 0xFFFF8000;
1616 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1625 inst |= (immed << IMM_LOW) & IMM_MASK;
1668 immed = 0;
1673 immed = exp.X_add_number;
1677 temp = immed & 0xFFFF8000;
1689 inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
1696 inst |= (immed << IMM_LOW) & IMM_MASK;
1712 immed = exp.X_add_number;
1714 if (immed != (immed % 32)) {
1716 immed = immed % 32;
1718 inst |= (immed << IMM_MBAR);
