Lines Matching refs:OPC2
87 #define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
93 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
157 #define CMPBR_INST(NAME, OPC1, OPC2, C4) \
165 {NAME, 2, ((0x300+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
168 {NAME, 3, ((0x310+OPC2)<<12)+C4, 8, CMPBR_INS | FMT_3 | RELAXABLE, \
348 #define LD_REG_INST(NAME, OPC1, OPC2, DISP) \
356 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP | REVERSE_MATCH, \
359 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
362 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
379 #define ST_REG_INST(NAME, OPC1, OPC2, DISP) \
385 {NAME, 1, 0x8+OPC2, 28, LD_STOR_INS | DISP, \
388 {NAME, 2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1, \
391 {NAME, 3, ((0x8+OPC2)<<8)+0xF, 20, LD_STOR_INS | FMT_1, \
428 #define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \
438 {NAME, 1, OPC2, SHIFT+4, CSTBIT_INS, {{OP,20}, {rbase,16}}}, \
492 #define BR_INST(NAME, OPC1, OPC2, INS_TYPE) \
496 {NAME, 3, OPC2, 20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}}
