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  /external/llvm/lib/Target/AMDGPU/Utils/
AMDGPUAsmUtils.h 14 namespace AMDGPU {
28 } // namespace AMDGPU
AMDGPUAsmUtils.cpp 12 namespace AMDGPU {
15 // This must be in sync with llvm::AMDGPU::SendMsg::Id enum members, see SIDefines.h.
35 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h.
55 // This must be in sync with llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_/LAST_, see SIDefines.h.
68 } // namespace AMDGPU
AMDGPUBaseInfo.h 1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
25 namespace AMDGPU {
64 } // end namespace AMDGPU
AMDGPUBaseInfo.cpp 1 //===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===//
10 #include "AMDGPU.h"
28 namespace AMDGPU {
128 return getIntegerAttribute(F, "amdgpu-max-work-group-size", 256);
152 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
156 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
160 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
167 case AMDGPU::FLAT_SCR:
169 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi
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  /external/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUFixupKinds.h 1 //===-- AMDGPUFixupKinds.h - AMDGPU Specific Fixup Entries ------*- C++ -*-===//
16 namespace AMDGPU {
  /external/llvm/lib/Target/AMDGPU/
AMDGPU.h 1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
116 namespace AMDGPU {
AMDGPUInstrInfo.h 1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
26 #define OPCODE_IS_ZERO_INT AMDGPU::PRED_SETE_INT
27 #define OPCODE_IS_NOT_ZERO_INT AMDGPU::PRED_SETNE_INT
28 #define OPCODE_IS_ZERO AMDGPU::PRED_SETE
29 #define OPCODE_IS_NOT_ZERO AMDGPU::PRED_SETNE
63 namespace AMDGPU {
66 } // End namespace AMDGPU
R600InstrInfo.h 323 namespace AMDGPU {
327 } //End namespace AMDGPU
AMDGPUInstrInfo.cpp 65 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
66 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
67 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
81 namespace AMDGPU {
108 int MCOp = AMDGPU::getMCOpcode(Opcode, subtargetEncodingFamily(ST));
SIInstrInfo.h 143 // DstRC, then AMDGPU::COPY is returned.
514 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
543 namespace AMDGPU {
569 } // End namespace AMDGPU
SIDefines.h 49 namespace AMDGPU {
108 namespace AMDGPU {
127 } // namespace AMDGPU
131 namespace AMDGPU {
207 } // namespace AMDGPU
  /external/clang/include/clang/Basic/
TargetBuiltins.h 76 /// \brief AMDGPU builtins
77 namespace AMDGPU {

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