1 /* ARM assembler/disassembler support. 2 Copyright (C) 2004-2014 Free Software Foundation, Inc. 3 4 This file is part of GDB and GAS. 5 6 GDB and GAS are free software; you can redistribute it and/or 7 modify it under the terms of the GNU General Public License as 8 published by the Free Software Foundation; either version 3, or (at 9 your option) any later version. 10 11 GDB and GAS are distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GDB or GAS; see the file COPYING3. If not, write to the 18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 /* The following bitmasks control CPU extensions: */ 22 #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ 23 #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ 24 #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ 25 #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ 26 #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ 27 #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ 28 #define ARM_EXT_V4T 0x00000040 /* Thumb. */ 29 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ 30 #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ 31 #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ 32 #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ 33 #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ 34 #define ARM_EXT_V6 0x00001000 /* ARM V6. */ 35 #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ 36 /* 0x00004000 Was ARM V6Z. */ 37 #define ARM_EXT_V8 0x00004000 /* is now ARMv8. */ 38 #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ 39 #define ARM_EXT_DIV 0x00010000 /* Integer division. */ 40 /* The 'M' in Arm V7M stands for Microcontroller. 41 On earlier architecture variants it stands for Multiply. */ 42 #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ 43 #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ 44 #define ARM_EXT_V7 0x00080000 /* Arm V7. */ 45 #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ 46 #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ 47 #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ 48 #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ 49 #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ 50 #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ 51 #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), 52 not in v7-M. */ 53 #define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ 54 #define ARM_EXT_SEC 0x10000000 /* Security extensions. */ 55 #define ARM_EXT_OS 0x20000000 /* OS Extensions. */ 56 #define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM 57 state. */ 58 #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ 59 60 /* Co-processor space extensions. */ 61 #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ 62 #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ 63 #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ 64 #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ 65 66 #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ 67 #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ 68 #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ 69 #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ 70 #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ 71 #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ 72 #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ 73 #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ 74 #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ 75 #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ 76 #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ 77 #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ 78 #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ 79 #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ 80 #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ 81 #define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ 82 #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ 83 #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ 84 #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ 85 86 /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) 87 defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, 88 ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add 89 three more to cover cores prior to ARM6. Finally, there are cores which 90 implement further extensions in the co-processor space. */ 91 #define ARM_AEXT_V1 ARM_EXT_V1 92 #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) 93 #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) 94 #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) 95 #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) 96 #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) 97 #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) 98 #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) 99 #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) 100 #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) 101 #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) 102 #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) 103 #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) 104 #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) 105 #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) 106 #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) 107 #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) 108 #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) 109 #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) 110 #define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC) 111 #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ 112 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ 113 | ARM_EXT_V6_DSP ) 114 #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) 115 #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) 116 #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) 117 #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) 118 #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) 119 #define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ 120 | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP) 121 #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) 122 #define ARM_AEXT_NOTM \ 123 (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ 124 | ARM_EXT_V6_DSP ) 125 #define ARM_AEXT_V6M_ONLY \ 126 ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) 127 #define ARM_AEXT_V6M \ 128 ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) 129 #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) 130 #define ARM_AEXT_V7M \ 131 ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ 132 & ~(ARM_AEXT_NOTM)) 133 #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) 134 #define ARM_AEXT_V7EM \ 135 (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) 136 #define ARM_AEXT_V8A \ 137 (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ 138 | ARM_EXT_VIRT | ARM_EXT_V8) 139 140 /* Processors with specific extensions in the co-processor space. */ 141 #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) 142 #define ARM_ARCH_IWMMXT \ 143 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) 144 #define ARM_ARCH_IWMMXT2 \ 145 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) 146 147 #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) 148 #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) 149 #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) 150 #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) 151 #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) 152 #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) 153 #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) 154 #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) 155 #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) 156 #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) 157 #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) 158 #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) 159 #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ 160 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ 161 | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) 162 #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) 163 164 /* Deprecated. */ 165 #define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) 166 167 #define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) 168 #define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) 169 170 #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) 171 #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) 172 #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) 173 #define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) 174 #define FPU_ARCH_VFP_V3D16_FP16 \ 175 ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) 176 #define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) 177 #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) 178 #define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) 179 #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) 180 #define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) 181 #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ 182 ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) 183 #define FPU_ARCH_NEON_FP16 \ 184 ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) 185 #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) 186 #define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) 187 #define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) 188 #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) 189 #define FPU_ARCH_NEON_VFP_V4 \ 190 ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) 191 #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) 192 #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) 193 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ 194 ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) 195 #define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8) 196 197 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) 198 199 #define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) 200 201 #define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) 202 #define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) 203 #define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) 204 #define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) 205 #define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) 206 #define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) 207 #define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) 208 #define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) 209 #define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) 210 #define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) 211 #define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) 212 #define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) 213 #define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) 214 #define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) 215 #define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) 216 #define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) 217 #define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) 218 #define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) 219 #define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) 220 #define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) 221 #define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) 222 #define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) 223 #define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) 224 #define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) 225 #define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) 226 #define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) 227 #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) 228 #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) 229 #define ARM_ARCH_V7VE ARM_FEATURE (ARM_AEXT_V7VE, 0) 230 #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) 231 #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) 232 #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) 233 #define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) 234 235 /* Some useful combinations: */ 236 #define ARM_ARCH_NONE ARM_FEATURE (0, 0) 237 #define FPU_NONE ARM_FEATURE (0, 0) 238 #define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ 239 #define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) 240 #define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) 241 /* v7-a+sec. */ 242 #define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0) 243 /* v7-a+mp+sec. */ 244 #define ARM_ARCH_V7A_MP_SEC \ 245 ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ 246 0) 247 /* v7-r+idiv. */ 248 #define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) 249 /* Features that are present in v6M and v6S-M but not other v6 cores. */ 250 #define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) 251 /* v8-a+fp. */ 252 #define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) 253 /* v8-a+simd (implies fp). */ 254 #define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ 255 FPU_ARCH_NEON_VFP_ARMV8) 256 /* v8-a+crypto (implies simd+fp). */ 257 #define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ 258 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) 259 260 /* There are too many feature bits to fit in a single word, so use a 261 structure. For simplicity we put all core features in one word and 262 everything else in the other. */ 263 typedef struct 264 { 265 unsigned long core; 266 unsigned long coproc; 267 } arm_feature_set; 268 269 #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ 270 (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) 271 272 #define ARM_CPU_IS_ANY(CPU) \ 273 ((CPU).core == ((arm_feature_set)ARM_ANY).core) 274 275 #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ 276 do { \ 277 (TARG).core = (F1).core | (F2).core; \ 278 (TARG).coproc = (F1).coproc | (F2).coproc; \ 279 } while (0) 280 281 #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ 282 do { \ 283 (TARG).core = (F1).core &~ (F2).core; \ 284 (TARG).coproc = (F1).coproc &~ (F2).coproc; \ 285 } while (0) 286 287 #define ARM_FEATURE(core, coproc) {(core), (coproc)} 288
