1 /* 2 * Copyright 2014, Michael Ellerman, IBM Corp. 3 * Licensed under GPLv2. 4 */ 5 6 #ifndef _SELFTESTS_POWERPC_REG_H 7 #define _SELFTESTS_POWERPC_REG_H 8 9 #define __stringify_1(x) #x 10 #define __stringify(x) __stringify_1(x) 11 12 #define mfspr(rn) ({unsigned long rval; \ 13 asm volatile("mfspr %0," _str(rn) \ 14 : "=r" (rval)); rval; }) 15 #define mtspr(rn, v) asm volatile("mtspr " _str(rn) ",%0" : \ 16 : "r" ((unsigned long)(v)) \ 17 : "memory") 18 19 #define mb() asm volatile("sync" : : : "memory"); 20 21 #define SPRN_MMCR2 769 22 #define SPRN_MMCRA 770 23 #define SPRN_MMCR0 779 24 #define MMCR0_PMAO 0x00000080 25 #define MMCR0_PMAE 0x04000000 26 #define MMCR0_FC 0x80000000 27 #define SPRN_EBBHR 804 28 #define SPRN_EBBRR 805 29 #define SPRN_BESCR 806 /* Branch event status & control register */ 30 #define SPRN_BESCRS 800 /* Branch event status & control set (1 bits set to 1) */ 31 #define SPRN_BESCRSU 801 /* Branch event status & control set upper */ 32 #define SPRN_BESCRR 802 /* Branch event status & control REset (1 bits set to 0) */ 33 #define SPRN_BESCRRU 803 /* Branch event status & control REset upper */ 34 35 #define BESCR_PMEO 0x1 /* PMU Event-based exception Occurred */ 36 #define BESCR_PME (0x1ul << 32) /* PMU Event-based exception Enable */ 37 #define BESCR_LME (0x1ul << 34) /* Load Monitor Enable */ 38 #define BESCR_LMEO (0x1ul << 2) /* Load Monitor Exception Occurred */ 39 40 #define SPRN_LMRR 813 /* Load Monitor Region Register */ 41 #define SPRN_LMSER 814 /* Load Monitor Section Enable Register */ 42 43 #define SPRN_PMC1 771 44 #define SPRN_PMC2 772 45 #define SPRN_PMC3 773 46 #define SPRN_PMC4 774 47 #define SPRN_PMC5 775 48 #define SPRN_PMC6 776 49 50 #define SPRN_SIAR 780 51 #define SPRN_SDAR 781 52 #define SPRN_SIER 768 53 54 #define SPRN_TEXASR 0x82 55 #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ 56 #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ 57 #define TEXASR_FS 0x08000000 58 #define SPRN_TAR 0x32f 59 60 #endif /* _SELFTESTS_POWERPC_REG_H */ 61
