1 //===- BlackfinISelLowering.h - Blackfin DAG Lowering Interface -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Blackfin uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef BLACKFIN_ISELLOWERING_H 16 #define BLACKFIN_ISELLOWERING_H 17 18 #include "llvm/Target/TargetLowering.h" 19 #include "Blackfin.h" 20 21 namespace llvm { 22 23 namespace BFISD { 24 enum { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 CALL, // A call instruction. 27 RET_FLAG, // Return with a flag operand. 28 Wrapper // Address wrapper 29 }; 30 } 31 32 class BlackfinTargetLowering : public TargetLowering { 33 public: 34 BlackfinTargetLowering(TargetMachine &TM); 35 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; } 36 virtual EVT getSetCCResultType(EVT VT) const; 37 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 38 virtual void ReplaceNodeResults(SDNode *N, 39 SmallVectorImpl<SDValue> &Results, 40 SelectionDAG &DAG) const; 41 42 ConstraintType getConstraintType(const std::string &Constraint) const; 43 44 /// Examine constraint string and operand type and determine a weight value. 45 /// The operand object must already have been set up with the operand type. 46 ConstraintWeight getSingleConstraintMatchWeight( 47 AsmOperandInfo &info, const char *constraint) const; 48 49 std::pair<unsigned, const TargetRegisterClass*> 50 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 51 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 52 const char *getTargetNodeName(unsigned Opcode) const; 53 54 private: 55 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 56 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const; 58 59 virtual SDValue 60 LowerFormalArguments(SDValue Chain, 61 CallingConv::ID CallConv, bool isVarArg, 62 const SmallVectorImpl<ISD::InputArg> &Ins, 63 DebugLoc dl, SelectionDAG &DAG, 64 SmallVectorImpl<SDValue> &InVals) const; 65 virtual SDValue 66 LowerCall(SDValue Chain, SDValue Callee, 67 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 68 const SmallVectorImpl<ISD::OutputArg> &Outs, 69 const SmallVectorImpl<SDValue> &OutVals, 70 const SmallVectorImpl<ISD::InputArg> &Ins, 71 DebugLoc dl, SelectionDAG &DAG, 72 SmallVectorImpl<SDValue> &InVals) const; 73 74 virtual SDValue 75 LowerReturn(SDValue Chain, 76 CallingConv::ID CallConv, bool isVarArg, 77 const SmallVectorImpl<ISD::OutputArg> &Outs, 78 const SmallVectorImpl<SDValue> &OutVals, 79 DebugLoc dl, SelectionDAG &DAG) const; 80 }; 81 } // end namespace llvm 82 83 #endif // BLACKFIN_ISELLOWERING_H 84
