1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __FVP_DEF_H__ 32 #define __FVP_DEF_H__ 33 34 /* Firmware Image Package */ 35 #define FIP_IMAGE_NAME "fip.bin" 36 #define FVP_PRIMARY_CPU 0x0 37 38 /* Memory location options for TSP */ 39 #define FVP_TRUSTED_SRAM_ID 0 40 #define FVP_TRUSTED_DRAM_ID 1 41 #define FVP_DRAM_ID 2 42 43 /* 44 * Some of the definitions in this file use the 'ull' suffix in order to avoid 45 * subtle integer overflow errors due to implicit integer type promotion when 46 * working with 32-bit values. 47 * 48 * The TSP linker script includes some of these definitions to define the BL3-2 49 * memory map, but the GNU LD does not support the 'ull' suffix, causing the 50 * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x) 51 * will add the 'ull' suffix only when the macro __LINKER__ is not defined 52 * (__LINKER__ is defined in the command line to preprocess the linker script). 53 * Constants in the linker script will not have the 'ull' suffix, but this is 54 * not a problem since the linker evaluates all constant expressions to 64 bit 55 * (assuming the target architecture is 64 bit). 56 */ 57 #ifndef __LINKER__ 58 #define MAKE_ULL(x) x##ull 59 #else 60 #define MAKE_ULL(x) x 61 #endif 62 63 /******************************************************************************* 64 * FVP memory map related constants 65 ******************************************************************************/ 66 67 #define FVP_TRUSTED_ROM_BASE 0x00000000 68 #define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 69 70 /* The first 4KB of Trusted SRAM are used as shared memory */ 71 #define FVP_SHARED_MEM_BASE 0x04000000 72 #define FVP_SHARED_MEM_SIZE 0x00001000 /* 4 KB */ 73 74 /* The remaining Trusted SRAM is used to load the BL images */ 75 #define FVP_TRUSTED_SRAM_BASE 0x04001000 76 #define FVP_TRUSTED_SRAM_SIZE 0x0003F000 /* 252 KB */ 77 78 #define FVP_TRUSTED_DRAM_BASE 0x06000000 79 #define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 80 81 #define FLASH0_BASE 0x08000000 82 #define FLASH0_SIZE 0x04000000 83 84 #define FLASH1_BASE 0x0c000000 85 #define FLASH1_SIZE 0x04000000 86 87 #define PSRAM_BASE 0x14000000 88 #define PSRAM_SIZE 0x04000000 89 90 #define VRAM_BASE 0x18000000 91 #define VRAM_SIZE 0x02000000 92 93 /* Aggregate of all devices in the first GB */ 94 #define DEVICE0_BASE 0x1a000000 95 #define DEVICE0_SIZE 0x12200000 96 97 #define DEVICE1_BASE 0x2f000000 98 #define DEVICE1_SIZE 0x200000 99 100 #define NSRAM_BASE 0x2e000000 101 #define NSRAM_SIZE 0x10000 102 103 #define DRAM1_BASE MAKE_ULL(0x80000000) 104 #define DRAM1_SIZE MAKE_ULL(0x80000000) 105 #define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) 106 107 /* Define the top 16 MB of DRAM1 as secure */ 108 #define DRAM1_SEC_SIZE MAKE_ULL(0x01000000) 109 #define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE) 110 #define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1) 111 112 #define DRAM1_NS_BASE DRAM1_BASE 113 #define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE) 114 #define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1) 115 116 #define DRAM_BASE DRAM1_BASE 117 #define DRAM_SIZE DRAM1_SIZE 118 119 #define DRAM2_BASE MAKE_ULL(0x880000000) 120 #define DRAM2_SIZE MAKE_ULL(0x780000000) 121 #define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) 122 123 #define PCIE_EXP_BASE 0x40000000 124 #define TZRNG_BASE 0x7fe60000 125 #define TZNVCTR_BASE 0x7fe70000 126 #define TZROOTKEY_BASE 0x7fe80000 127 128 /* Memory mapped Generic timer interfaces */ 129 #define SYS_CNTCTL_BASE 0x2a430000 130 #define SYS_CNTREAD_BASE 0x2a800000 131 #define SYS_TIMCTL_BASE 0x2a810000 132 133 /* V2M motherboard system registers & offsets */ 134 #define VE_SYSREGS_BASE 0x1c010000 135 #define V2M_SYS_ID 0x0 136 #define V2M_SYS_SWITCH 0x4 137 #define V2M_SYS_LED 0x8 138 #define V2M_SYS_CFGDATA 0xa0 139 #define V2M_SYS_CFGCTRL 0xa4 140 #define V2M_SYS_CFGSTATUS 0xa8 141 142 #define CFGCTRL_START (1 << 31) 143 #define CFGCTRL_RW (1 << 30) 144 #define CFGCTRL_FUNC_SHIFT 20 145 #define CFGCTRL_FUNC(fn) (fn << CFGCTRL_FUNC_SHIFT) 146 #define FUNC_CLK_GEN 0x01 147 #define FUNC_TEMP 0x04 148 #define FUNC_DB_RESET 0x05 149 #define FUNC_SCC_CFG 0x06 150 #define FUNC_SHUTDOWN 0x08 151 #define FUNC_REBOOT 0x09 152 153 /* Load address of BL33 in the FVP port */ 154 #define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ 155 156 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 157 #define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 158 159 /* 160 * V2M sysled bit definitions. The values written to this 161 * register are defined in arch.h & runtime_svc.h. Only 162 * used by the primary cpu to diagnose any cold boot issues. 163 * 164 * SYS_LED[0] - Security state (S=0/NS=1) 165 * SYS_LED[2:1] - Exception Level (EL3-EL0) 166 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 167 * 168 */ 169 #define SYS_LED_SS_SHIFT 0x0 170 #define SYS_LED_EL_SHIFT 0x1 171 #define SYS_LED_EC_SHIFT 0x3 172 173 #define SYS_LED_SS_MASK 0x1 174 #define SYS_LED_EL_MASK 0x3 175 #define SYS_LED_EC_MASK 0x1f 176 177 /* V2M sysid register bits */ 178 #define SYS_ID_REV_SHIFT 28 179 #define SYS_ID_HBI_SHIFT 16 180 #define SYS_ID_BLD_SHIFT 12 181 #define SYS_ID_ARCH_SHIFT 8 182 #define SYS_ID_FPGA_SHIFT 0 183 184 #define SYS_ID_REV_MASK 0xf 185 #define SYS_ID_HBI_MASK 0xfff 186 #define SYS_ID_BLD_MASK 0xf 187 #define SYS_ID_ARCH_MASK 0xf 188 #define SYS_ID_FPGA_MASK 0xff 189 190 #define SYS_ID_BLD_LENGTH 4 191 192 #define HBI_FVP_BASE 0x020 193 #define REV_FVP_BASE_V0 0x0 194 195 #define HBI_FOUNDATION 0x010 196 #define REV_FOUNDATION_V2_0 0x0 197 #define REV_FOUNDATION_V2_1 0x1 198 199 #define BLD_GIC_VE_MMAP 0x0 200 #define BLD_GIC_A53A57_MMAP 0x1 201 202 #define ARCH_MODEL 0x1 203 204 /* FVP Power controller base address*/ 205 #define PWRC_BASE 0x1c100000 206 207 208 /******************************************************************************* 209 * CCI-400 related constants 210 ******************************************************************************/ 211 #define CCI400_BASE 0x2c090000 212 #define CCI400_SL_IFACE3_CLUSTER_IX 0 213 #define CCI400_SL_IFACE4_CLUSTER_IX 1 214 215 /******************************************************************************* 216 * GIC-400 & interrupt handling related constants 217 ******************************************************************************/ 218 /* VE compatible GIC memory map */ 219 #define VE_GICD_BASE 0x2c001000 220 #define VE_GICC_BASE 0x2c002000 221 #define VE_GICH_BASE 0x2c004000 222 #define VE_GICV_BASE 0x2c006000 223 224 /* Base FVP compatible GIC memory map */ 225 #define BASE_GICD_BASE 0x2f000000 226 #define BASE_GICR_BASE 0x2f100000 227 #define BASE_GICC_BASE 0x2c000000 228 #define BASE_GICH_BASE 0x2c010000 229 #define BASE_GICV_BASE 0x2c02f000 230 231 #define IRQ_TZ_WDOG 56 232 #define IRQ_SEC_PHY_TIMER 29 233 #define IRQ_SEC_SGI_0 8 234 #define IRQ_SEC_SGI_1 9 235 #define IRQ_SEC_SGI_2 10 236 #define IRQ_SEC_SGI_3 11 237 #define IRQ_SEC_SGI_4 12 238 #define IRQ_SEC_SGI_5 13 239 #define IRQ_SEC_SGI_6 14 240 #define IRQ_SEC_SGI_7 15 241 242 /******************************************************************************* 243 * PL011 related constants 244 ******************************************************************************/ 245 #define PL011_UART0_BASE 0x1c090000 246 #define PL011_UART1_BASE 0x1c0a0000 247 #define PL011_UART2_BASE 0x1c0b0000 248 #define PL011_UART3_BASE 0x1c0c0000 249 250 #define PL011_BAUDRATE 115200 251 252 #define PL011_UART0_CLK_IN_HZ 24000000 253 #define PL011_UART1_CLK_IN_HZ 24000000 254 #define PL011_UART2_CLK_IN_HZ 24000000 255 #define PL011_UART3_CLK_IN_HZ 24000000 256 257 /******************************************************************************* 258 * TrustZone address space controller related constants 259 ******************************************************************************/ 260 #define TZC400_BASE 0x2a4a0000 261 262 /* 263 * The NSAIDs for this platform as used to program the TZC400. 264 */ 265 266 /* NSAIDs used by devices in TZC filter 0 on FVP */ 267 #define FVP_NSAID_DEFAULT 0 268 #define FVP_NSAID_PCI 1 269 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 270 #define FVP_NSAID_AP 9 /* Application Processors */ 271 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 272 273 /* NSAIDs used by devices in TZC filter 2 on FVP */ 274 #define FVP_NSAID_HDLCD0 2 275 #define FVP_NSAID_CLCD 7 276 277 /******************************************************************************* 278 * Shared Data 279 ******************************************************************************/ 280 281 /* Entrypoint mailboxes */ 282 #define MBOX_BASE FVP_SHARED_MEM_BASE 283 #define MBOX_SIZE 0x200 284 285 /* Base address where parameters to BL31 are stored */ 286 #define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) 287 288 #endif /* __FVP_DEF_H__ */ 289
