1 /** @file 2 * 3 * Copyright (c) 2014, Linaro Limited. All rights reserved. 4 * Copyright (c) 2014, Hisilicon Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 17 #ifndef __DWSD_H__ 18 #define __DWSD_H__ 19 20 #include <Protocol/EmbeddedGpio.h> 21 22 // DW MMC Registers 23 #define DWSD_CTRL ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x000) 24 #define DWSD_PWREN ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x004) 25 #define DWSD_CLKDIV ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x008) 26 #define DWSD_CLKSRC ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x00c) 27 #define DWSD_CLKENA ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x010) 28 #define DWSD_TMOUT ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x014) 29 #define DWSD_CTYPE ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x018) 30 #define DWSD_BLKSIZ ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x01c) 31 #define DWSD_BYTCNT ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x020) 32 #define DWSD_INTMASK ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x024) 33 #define DWSD_CMDARG ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x028) 34 #define DWSD_CMD ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x02c) 35 #define DWSD_RESP0 ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x030) 36 #define DWSD_RESP1 ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x034) 37 #define DWSD_RESP2 ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x038) 38 #define DWSD_RESP3 ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x03c) 39 #define DWSD_RINTSTS ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x044) 40 #define DWSD_STATUS ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x048) 41 #define DWSD_FIFOTH ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x04c) 42 #define DWSD_TCBCNT ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x05c) 43 #define DWSD_TBBCNT ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x060) 44 #define DWSD_DEBNCE ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x064) 45 #define DWSD_UHSREG ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x074) 46 #define DWSD_BMOD ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x080) 47 #define DWSD_DBADDR ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x088) 48 #define DWSD_IDSTS ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x08c) 49 #define DWSD_IDINTEN ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x090) 50 #define DWSD_DSCADDR ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x094) 51 #define DWSD_BUFADDR ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x098) 52 #define DWSD_CARDTHRCTL ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x100) 53 #define DWSD_FIFO_START ((UINT32)PcdGet32 (PcdDwSdDxeBaseAddress) + 0x200) 54 55 #define CMD_UPDATE_CLK 0x80202000 56 #define CMD_START_BIT (1 << 31) 57 58 #define MMC_8BIT_MODE (1 << 16) 59 60 #define BIT_CMD_RESPONSE_EXPECT (1 << 6) 61 #define BIT_CMD_LONG_RESPONSE (1 << 7) 62 #define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) 63 #define BIT_CMD_DATA_EXPECTED (1 << 9) 64 #define BIT_CMD_READ (0 << 10) 65 #define BIT_CMD_WRITE (1 << 10) 66 #define BIT_CMD_BLOCK_TRANSFER (0 << 11) 67 #define BIT_CMD_STREAM_TRANSFER (1 << 11) 68 #define BIT_CMD_SEND_AUTO_STOP (1 << 12) 69 #define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 70 #define BIT_CMD_STOP_ABORT_CMD (1 << 14) 71 #define BIT_CMD_SEND_INIT (1 << 15) 72 #define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) 73 #define BIT_CMD_READ_CEATA_DEVICE (1 << 22) 74 #define BIT_CMD_CCS_EXPECTED (1 << 23) 75 #define BIT_CMD_ENABLE_BOOT (1 << 24) 76 #define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) 77 #define BIT_CMD_DISABLE_BOOT (1 << 26) 78 #define BIT_CMD_MANDATORY_BOOT (0 << 27) 79 #define BIT_CMD_ALTERNATE_BOOT (1 << 27) 80 #define BIT_CMD_VOLT_SWITCH (1 << 28) 81 #define BIT_CMD_USE_HOLD_REG (1 << 29) 82 #define BIT_CMD_START (1 << 31) 83 84 #define DWSD_INT_EBE (1 << 15) /* End-bit Err */ 85 #define DWSD_INT_SBE (1 << 13) /* Start-bit Err */ 86 #define DWSD_INT_HLE (1 << 12) /* Hardware-lock Err */ 87 #define DWSD_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ 88 #define DWSD_INT_DRT (1 << 9) /* Data timeout */ 89 #define DWSD_INT_RTO (1 << 8) /* Response timeout */ 90 #define DWSD_INT_DCRC (1 << 7) /* Data CRC err */ 91 #define DWSD_INT_RCRC (1 << 6) /* Response CRC err */ 92 #define DWSD_INT_RXDR (1 << 5) 93 #define DWSD_INT_TXDR (1 << 4) 94 #define DWSD_INT_DTO (1 << 3) /* Data trans over */ 95 #define DWSD_INT_CMD_DONE (1 << 2) 96 #define DWSD_INT_RE (1 << 1) 97 98 #define DWSD_IDMAC_DES0_DIC (1 << 1) 99 #define DWSD_IDMAC_DES0_LD (1 << 2) 100 #define DWSD_IDMAC_DES0_FS (1 << 3) 101 #define DWSD_IDMAC_DES0_CH (1 << 4) 102 #define DWSD_IDMAC_DES0_ER (1 << 5) 103 #define DWSD_IDMAC_DES0_CES (1 << 30) 104 #define DWSD_IDMAC_DES0_OWN (1 << 31) 105 #define DWSD_IDMAC_DES1_BS1(x) ((x) & 0x1fff) 106 #define DWSD_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) 107 #define DWSD_IDMAC_SWRESET (1 << 0) 108 #define DWSD_IDMAC_FB (1 << 1) 109 #define DWSD_IDMAC_ENABLE (1 << 7) 110 111 #define EMMC_FIX_RCA 6 112 113 /* bits in MMC0_CTRL */ 114 #define DWSD_CTRL_RESET (1 << 0) 115 #define DWSD_CTRL_FIFO_RESET (1 << 1) 116 #define DWSD_CTRL_DMA_RESET (1 << 2) 117 #define DWSD_CTRL_INT_EN (1 << 4) 118 #define DWSD_CTRL_DMA_EN (1 << 5) 119 #define DWSD_CTRL_IDMAC_EN (1 << 25) 120 #define DWSD_CTRL_RESET_ALL (DWSD_CTRL_RESET | DWSD_CTRL_FIFO_RESET | DWSD_CTRL_DMA_RESET) 121 122 #define DWSD_STS_DATA_BUSY (1 << 9) 123 124 #define DWSD_FIFO_TWMARK(x) (x & 0xfff) 125 #define DWSD_FIFO_RWMARK(x) ((x & 0x1ff) << 16) 126 #define DWSD_DMA_BURST_SIZE(x) ((x & 0x7) << 28) 127 128 #define DWSD_CARD_RD_THR(x) ((x & 0xfff) << 16) 129 #define DWSD_CARD_RD_THR_EN (1 << 0) 130 131 #endif // __DWSD_H__ 132
