| /external/llvm/lib/Target/AMDGPU/ |
| SILowerI1Copies.cpp | 102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
105 if (DstRC == &AMDGPU::VReg_1RegClass &&
132 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
|
| SIFixSGPRCopies.cpp | 143 const TargetRegisterClass *DstRC =
148 return std::make_pair(SrcRC, DstRC);
152 const TargetRegisterClass *DstRC,
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
158 const TargetRegisterClass *DstRC,
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
193 const TargetRegisterClass *SrcRC, *DstRC;
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
204 MRI.setRegClass(DstReg, DstRC);
[all...] |
| SIInstrInfo.cpp | 336 const TargetRegisterClass *DstRC = MRI.getRegClass(FirstDst->getReg());
338 return (NumLoads * DstRC->getSize()) <= LoadClusterThreshold;
522 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
524 if (DstRC->getSize() == 4) {
525 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
526 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
528 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 131 const TargetRegisterClass *DstRC =
141 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
|
| PPCVSXSwapRemoval.cpp | 886 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
887 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
162 DstRC = MRI->getRegClass(VRBase);
165 DstRC = UseRC;
167 DstRC = TLI->getRegClassFor(VT);
176 VRBase = MRI->createVirtualRegister(DstRC);
333 const TargetRegisterClass *DstRC = nullptr;
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
336 assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) &&
338 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 137 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
142 DstRC = MRI->getRegClass(VRBase);
145 DstRC = UseRC;
147 DstRC = TLI->getRegClassFor(VT);
156 VRBase = MRI->createVirtualRegister(DstRC);
294 const TargetRegisterClass *DstRC = 0;
296 DstRC = TII->getRegClass(*II, IIOpNum, TRI);
297 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
299 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize))
[all...] |
| /external/llvm/lib/CodeGen/ |
| DetectDeadLanes.cpp | 157 const TargetRegisterClass *DstRC,
162 if (DstRC == SrcRC)
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
193 return !TRI.getCommonSubClass(SrcRC, DstRC);
441 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
442 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
490 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
491 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO)
[all...] |
| PeepholeOptimizer.cpp | 428 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
429 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
430 if (!DstRC)
536 MRI->constrainRegClass(DstReg, DstRC);
[all...] |
| RegisterCoalescer.cpp | 353 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
361 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
368 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
372 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
375 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
390 CrossClass = NewRC != DstRC || NewRC != SrcRC;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterCoalescer.cpp | 157 const TargetRegisterClass *DstRC,
290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
291 if (!TRI.getCommonSubClass(DstRC, SrcRC))
307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
314 CrossClass = NewRC != DstRC || NewRC != SrcRC;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
