1 /* NDS32-specific support for 32-bit ELF. 2 Copyright (C) 2012-2014 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 23 #ifndef NDS32_ASM_H 24 #define NDS32_ASM_H 25 26 /* Constant values for assembler. */ 27 enum 28 { 29 /* Error code for assembling an instruction. */ 30 NASM_OK = 0, 31 NASM_ERR_UNKNOWN_OP, 32 NASM_ERR_SYNTAX, 33 NASM_ERR_OPERAND, 34 NASM_ERR_OUT_OF_RANGE, 35 NASM_ERR_REG_REDUCED, 36 NASM_ERR_JUNK_EOL, 37 38 /* Results of parse_operand. */ 39 NASM_R_CONST, 40 NASM_R_SYMBOL, 41 NASM_R_ILLEGAL, 42 43 /* Flags for open description. */ 44 NASM_OPEN_ARCH_V1 = 0x0, 45 NASM_OPEN_ARCH_V2 = 0x1, 46 NASM_OPEN_ARCH_V3 = 0x2, 47 NASM_OPEN_ARCH_V3M = 0x3, 48 NASM_OPEN_ARCH_MASK = 0xf, 49 NASM_OPEN_REDUCED_REG = 0x10, 50 51 /* Common attributes. */ 52 NASM_ATTR_ISA_V1 = 0x01, 53 NASM_ATTR_ISA_V2 = 0x02, 54 NASM_ATTR_ISA_V3 = 0x04, 55 NASM_ATTR_ISA_V3M = 0x08, 56 NASM_ATTR_ISA_ALL = 0x0f, 57 58 /* Attributes for instructions. */ 59 NASM_ATTR_MAC = 0x0000100, 60 NASM_ATTR_DIV = 0x0000200, 61 NASM_ATTR_FPU = 0x0000400, 62 NASM_ATTR_FPU_SP_EXT = 0x0000800, 63 NASM_ATTR_FPU_DP_EXT = 0x0001000, 64 NASM_ATTR_STR_EXT = 0x0002000, 65 NASM_ATTR_PERF_EXT = 0x0004000, 66 NASM_ATTR_PERF2_EXT = 0x0008000, 67 NASM_ATTR_AUDIO_ISAEXT = 0x0010000, 68 NASM_ATTR_IFC_EXT = 0x0020000, 69 NASM_ATTR_EX9_EXT = 0x0040000, 70 NASM_ATTR_FPU_FMA = 0x0080000, 71 NASM_ATTR_DXREG = 0x0100000, 72 NASM_ATTR_BRANCH = 0x0200000, 73 NASM_ATTR_SATURATION_EXT = 0x0400000, 74 NASM_ATTR_PCREL = 0x0800000, 75 NASM_ATTR_GPREL = 0x1000000, 76 77 /* Attributes for relocations. */ 78 NASM_ATTR_HI20 = 0x10000000, 79 NASM_ATTR_LO12 = 0x20000000, 80 NASM_ATTR_LO20 = 0x40000000, 81 82 /* Attributes for registers. */ 83 NASM_ATTR_RDREG = 0x000100 84 }; 85 86 enum 87 { 88 /* This is a field (operand) of just a separator char. */ 89 SYN_FIELD = 0x100, 90 91 /* This operand is used for input or output. (define or use) */ 92 SYN_INPUT = 0x1000, 93 SYN_OUTPUT = 0x2000, 94 SYN_LOPT = 0x4000, 95 SYN_ROPT = 0x8000, 96 97 /* Hardware resources. */ 98 HW_GPR = 0, 99 HW_USR, 100 HW_DXR, 101 HW_SR, 102 HW_FSR, 103 HW_FDR, 104 HW_CP, /* Co-processor ID. */ 105 HW_CPR, /* Co-processor registers. */ 106 HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */ 107 HW_ABM, /* [ab]m? flag for LSMWZB. */ 108 HW_DTITON, 109 HW_DTITOFF, 110 HW_DPREF_ST, 111 HW_CCTL_ST0, 112 HW_CCTL_ST1, 113 HW_CCTL_ST2, 114 HW_CCTL_ST3, 115 HW_CCTL_ST4, 116 HW_CCTL_ST5, 117 HW_CCTL_LV, 118 HW_TLBOP_ST, 119 HW_STANDBY_ST, 120 HW_MSYNC_ST, 121 HW_AEXT_IM_I, 122 HW_AEXT_IM_M, 123 HW_AEXT_ACC, 124 HW_AEXT_ARIDX, 125 HW_AEXT_ARIDX2, 126 HW_AEXT_ARIDXI, 127 _HW_LAST, 128 /* TODO: Maybe we should add a new type to distinguish address and 129 const int. Only the former allows symbols and relocations. */ 130 HW_INT, 131 HW_UINT 132 }; 133 134 /* for audio-extension. */ 135 enum 136 { 137 N32_AEXT_AMADD = 0, 138 N32_AEXT_AMSUB, 139 N32_AEXT_AMULT, 140 N32_AEXT_AMFAR, 141 N32_AEXT_AMADDS, 142 N32_AEXT_AMSUBS, 143 N32_AEXT_AMULTS, 144 N32_AEXT_AMNEGS, 145 N32_AEXT_AADDL, 146 N32_AEXT_AMTARI, 147 N32_AEXT_AMAWBS = 0x0c, 148 N32_AEXT_AMAWTS, 149 N32_AEXT_AMWBS, 150 N32_AEXT_AMWTS, 151 N32_AEXT_AMABBS, 152 N32_AEXT_AMABTS, 153 N32_AEXT_AMATBS, 154 N32_AEXT_AMATTS, 155 N32_AEXT_AMBBS, 156 N32_AEXT_AMBTS, 157 N32_AEXT_AMTBS, 158 N32_AEXT_AMTTS 159 }; 160 161 /* Macro for instruction attribute. */ 162 #define ATTR(attr) NASM_ATTR_ ## attr 163 #define ATTR_NONE 0 164 #define ATTR_PCREL (ATTR (PCREL) | ATTR (BRANCH)) 165 166 #define ATTR_ALL (ATTR (ISA_ALL)) 167 #define ATTR_V2UP (ATTR_ALL & ~(ATTR (ISA_V1))) 168 #define ATTR_V3MUP (ATTR (ISA_V3) | ATTR (ISA_V3M)) 169 #define ATTR_V3 (ATTR (ISA_V3)) 170 #define ATTR_V3MEX_V1 (ATTR_ALL & ~(ATTR (ISA_V3M))) 171 #define ATTR_V3MEX_V2 (ATTR_V2UP & ~(ATTR (ISA_V3M))) 172 173 /* Lexical element in parsed syntax. */ 174 typedef int lex_t; 175 176 /* Common header for hash entries. */ 177 struct nds32_hash_entry 178 { 179 const char *name; 180 }; 181 182 typedef struct nds32_keyword 183 { 184 const char *name; 185 int value; 186 uint64_t attr; 187 } keyword_t; 188 189 typedef struct nds32_opcode 190 { 191 /* Opcode for the instruction. */ 192 const char *opcode; 193 /* Human readable string of this instruction. */ 194 const char *instruction; 195 /* Base value of this instruction. */ 196 uint32_t value; 197 /* The byte-size of the instruction. */ 198 int isize; 199 /* Attributes of this instruction. */ 200 uint64_t attr; 201 /* Implicit define/use. */ 202 uint64_t defuse; 203 /* Parsed string for assembling. */ 204 lex_t *syntax; 205 /* Number of variant. */ 206 int variant; 207 /* Next form of the same mnemonic. */ 208 struct nds32_opcode *next; 209 210 /* TODO: Extra constrains and verification. 211 For example, `mov55 $sp, $sp' is not allowed in v3. */ 212 } opcode_t; 213 214 typedef struct nds32_asm_insn 215 { 216 /* Assembled instruction bytes. */ 217 uint32_t insn; 218 /* The opcode structure for this instruction. */ 219 struct nds32_opcode *opcode; 220 /* The field need special fix-up, used for relocation. */ 221 const struct nds32_field *field; 222 /* Attributes for relocation. */ 223 uint64_t attr; 224 /* Application-dependent data, e.g., expression. */ 225 void *info; 226 /* Input/output registers. */ 227 uint64_t defuse; 228 } nds32_asm_insn_t; 229 230 typedef struct nds32_asm_desc 231 { 232 /* The callback provided by assembler user for parse an operand, 233 e.g., parse integer. */ 234 int (*parse_operand) (struct nds32_asm_desc *, 235 struct nds32_asm_insn *, 236 char **, int64_t *); 237 238 /* Result of assembling. */ 239 int result; 240 241 /* The mach for this assembling. */ 242 int mach; 243 244 int flags; 245 } nds32_asm_desc_t; 246 247 /* The field information for an operand. */ 248 typedef struct nds32_field 249 { 250 /* Name of the field. */ 251 const char *name; 252 253 int bitpos; 254 int bitsize; 255 int shift; 256 int hw_res; 257 258 int (*parse) (struct nds32_asm_desc *, 259 struct nds32_asm_insn *, 260 char **, int64_t *); 261 } field_t; 262 263 extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *); 264 extern void nds32_asm_init (nds32_asm_desc_t *, int); 265 266 #define OP6(op6) (N32_OP6_ ## op6 << 25) 267 268 #define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub) 269 #define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub) 270 #define JREG_RET (1 << 5) 271 #define JREG_IFC (1 << 6) 272 #define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16)) 273 #define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub) 274 #define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub) 275 #define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub) 276 #define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub) 277 #define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub) 278 #define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12)) 279 #define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6)) 280 #define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \ 281 | (N32_FPU_FS1_F2OP_ ## sub << 10)) 282 #define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6)) 283 #define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6)) 284 #define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \ 285 | (N32_FPU_FD1_F2OP_ ## sub << 10)) 286 #define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6)) 287 #define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6)) 288 #define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \ 289 | (N32_FPU_MFCP_XR_ ## sub << 10)) 290 #define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6)) 291 #define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \ 292 | (N32_FPU_MTCP_XR_ ## sub << 10)) 293 #define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub) 294 #define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7) 295 #define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20)) 296 297 #endif 298
