| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonInstPrinter.h | 28 explicit HexagonInstPrinter(MCAsmInfo const &MAI, MCInstrInfo const &MII,
77 MCInstrInfo const &getMII() const { return MII; }
84 MCInstrInfo const &MII;
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBundleIterator.h | 28 instr_iterator MII;
31 MachineInstrBundleIterator(instr_iterator MI) : MII(MI) {}
33 MachineInstrBundleIterator(Ty &MI) : MII(MI) {
38 MachineInstrBundleIterator(Ty *MI) : MII(MI) {
47 : MII(I.getInstrIterator()) {}
48 MachineInstrBundleIterator() : MII(nullptr) {}
50 Ty &operator*() const { return *MII; }
54 operator Ty *() const { return MII.getNodePtrUnchecked(); }
57 return MII == X.MII;
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstPrinter.h | 45 const MCInstrInfo &MII;
61 MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
63 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri), UseMarkup(0),
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCFGOptimizer.cpp | 112 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
113 if (MII != MBB->end()) {
114 MachineInstr &MI = *MII;
|
| HexagonFixupHwLoops.cpp | 71 MachineBasicBlock::iterator &MII);
138 MachineBasicBlock::iterator MII = MBB.begin();
140 while (MII != MIE) {
141 InstOffset += HII->getSize(&*MII);
142 if (MII->isDebugValue()) {
143 ++MII;
146 if (isHardwareLoop(*MII)) {
147 assert(MII->getOperand(0).isMBB() &&
149 int diff = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
151 useExtLoopInstr(MF, MII);
[all...] |
| HexagonSplitConst32AndConst64.cpp | 86 MachineBasicBlock::iterator MII = MBB->begin();
88 while (MII != MIE) {
89 MachineInstr &MI = *MII;
96 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::LO), DestReg)
98 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::HI), DestReg)
102 MII = MBB->erase(&MI);
120 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
123 MII = MBB->erase(&MI);
146 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
149 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi)
[all...] |
| HexagonAsmPrinter.cpp | 591 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
594 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
595 if (MII->getOpcode() == TargetOpcode::DBG_VALUE ||
596 MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
599 HexagonLowerToMC(MCII, &*MII, MCB, *this);
|
| HexagonVLIWPacketizer.cpp | 336 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
367 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
371 if (!HII->isV60VectorInstruction(&*MII))
389 MachineInstr &MJ = *MII;
419 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
699 MachineBasicBlock::iterator &MII) {
726 const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
777 if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 55 const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
56 if (!MII)
86 Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
92 TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
308 const MCInstrInfo *MII = DC->getInstrInfo();
313 Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
|
| Disassembler.h | 69 std::unique_ptr<const llvm::MCInstrInfo> MII;
91 const MCInstrInfo *mII, llvm::MCContext *ctx,
99 MII.reset(mII);
114 const MCInstrInfo *getInstrInfo() const { return MII.get(); }
|
| /external/llvm/include/llvm/Target/ |
| TargetMachine.h | 99 const MCInstrInfo *MII;
158 const MCInstrInfo *getMCInstrInfo() const { return MII; }
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 52 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
53 MIE = MBB->instr_end(); MII != MIE; ) {
54 MachineInstr *MI = &*MII;
59 while (++MII != MIE && MII->isBundledWithPred()) {
60 MII->unbundleFromPred();
61 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
62 MachineOperand &MO = MII->getOperand(i);
73 ++MII;
240 MachineBasicBlock::instr_iterator MII = MBB.instr_begin()
[all...] |
| RegAllocFast.cpp | 810 MachineBasicBlock::iterator MII = MBB->begin();
815 definePhysReg(*MII, LI.PhysReg, regReserved);
821 while (MII != MBB->end()) {
822 MachineInstr *MI = &*MII++;
[all...] |
| InlineSpiller.cpp | 381 MachineBasicBlock::iterator MII;
383 MII = MBB->SkipPHIsAndLabels(MBB->begin());
387 MII = DefMI;
388 ++MII;
391 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
393 --MII; // Point to store instruction.
394 LIS.InsertMachineInstrInMaps(*MII);
395 DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
397 HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
[all...] |
| LiveIntervalAnalysis.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600Packetizer.cpp | 186 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
187 if (getSlot(*MII) == getSlot(*MIJ))
189 // Does MII and MIJ share the same pred_sel ?
190 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
192 unsigned PredI = (OpI > -1)?MII->getOperand(OpI).getReg():0,
204 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
211 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
213 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);
|
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 315 MachineBasicBlock::iterator MII = MI;
316 MII = std::prev(MII);
317 MachineInstr &MI2 = *MII;
318 MII = std::prev(MII);
319 MachineInstr &MI1 = *MII;
335 MachineBasicBlock::reverse_iterator MII = MBB.rbegin(), E = MBB.rend();
336 while (MII != E) {
337 MachineInstr *MI = &*MII;
[all...] |
| Thumb2SizeReduction.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 247 MachineBasicBlock::iterator MII = MI;
248 MII = llvm::prior(MII);
249 MachineInstr &MI2 = *MII;
250 MII = llvm::prior(MII);
251 MachineInstr &MI1 = *MII;
267 MachineBasicBlock::reverse_iterator MII = MBB.rbegin(), E = MBB.rend();
268 while (MII != E) {
269 MachineInstr *MI = &*MII;
[all...] |
| Thumb2SizeReduction.cpp | 821 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
823 for (; MII != E; MII = NextMII) {
824 NextMII = llvm::next(MII);
826 MachineInstr *MI = &*MII;
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 100 const void *mii) {
101 const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
102 return MII->getName(Opcode);
135 std::unique_ptr<const MCInstrInfo> MII;
138 std::unique_ptr<const MCInstrInfo> MII);
154 std::unique_ptr<const MCInstrInfo> MII)
155 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
228 (const void *)MII.get(), Address, fMode)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegAllocFast.cpp | 760 MachineBasicBlock::iterator MII = MBB->begin();
766 definePhysReg(MII, *I, regReserved);
772 while (MII != MBB->end()) {
773 MachineInstr *MI = MII++;
[all...] |
| InlineSpiller.cpp | 715 MachineBasicBlock::iterator MII;
717 MII = MBB->SkipPHIsAndLabels(MBB->begin());
721 MII = DefMI;
722 ++MII;
725 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
727 --MII; // Point to store instruction.
728 LIS.InsertMachineInstrInMaps(MII);
729 VRM.addSpillSlotUse(StackSlot, MII);
730 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
[all...] |
| /external/clang/lib/Lex/ |
| PPDirectives.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 244 const MCInstrInfo &MII;
292 const MCInstrInfo &MII, const MCTargetOptions &Options)
293 : MCTargetAsmParser(Options, STI), MII(MII) {
[all...] |
