1 /* 2 * Copyright (c) 2014, Hisilicon Ltd. 3 * Copyright (c) 2014, Linaro Ltd. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __DW_MMC_H__ 33 #define __DW_MMC_H__ 34 35 #include <stdint.h> 36 37 #define MMC0_CTRL (MMC0_BASE + 0x000) 38 #define MMC0_CLKDIV (MMC0_BASE + 0x008) 39 #define MMC0_CLKSRC (MMC0_BASE + 0x00c) 40 #define MMC0_CLKENA (MMC0_BASE + 0x010) 41 #define MMC0_TMOUT (MMC0_BASE + 0x014) 42 #define MMC0_CTYPE (MMC0_BASE + 0x018) 43 #define MMC0_BLKSIZ (MMC0_BASE + 0x01c) 44 #define MMC0_BYTCNT (MMC0_BASE + 0x020) 45 #define MMC0_INTMASK (MMC0_BASE + 0x024) 46 #define MMC0_CMDARG (MMC0_BASE + 0x028) 47 #define MMC0_CMD (MMC0_BASE + 0x02c) 48 #define MMC0_RESP0 (MMC0_BASE + 0x030) 49 #define MMC0_RESP1 (MMC0_BASE + 0x034) 50 #define MMC0_RESP2 (MMC0_BASE + 0x038) 51 #define MMC0_RESP3 (MMC0_BASE + 0x03c) 52 #define MMC0_RINTSTS (MMC0_BASE + 0x044) 53 #define MMC0_STATUS (MMC0_BASE + 0x048) 54 #define MMC0_FIFOTH (MMC0_BASE + 0x04c) 55 #define MMC0_DEBNCE (MMC0_BASE + 0x064) 56 #define MMC0_UHSREG (MMC0_BASE + 0x074) 57 #define MMC0_BMOD (MMC0_BASE + 0x080) 58 #define MMC0_DBADDR (MMC0_BASE + 0x088) 59 #define MMC0_IDSTS (MMC0_BASE + 0x08c) 60 #define MMC0_IDINTEN (MMC0_BASE + 0x090) 61 #define MMC0_DSCADDR (MMC0_BASE + 0x094) 62 #define MMC0_BUFADDR (MMC0_BASE + 0x098) 63 #define MMC0_CARDTHRCTL (MMC0_BASE + 0X100) 64 65 #define CMD_UPDATE_CLK 0x80202000 66 #define CMD_START_BIT (1 << 31) 67 68 #define MMC_8BIT_MODE (1 << 16) 69 70 #define MMC_BLOCK_SIZE 512 71 72 #define BIT_CMD_RESPONSE_EXPECT (1 << 6) 73 #define BIT_CMD_LONG_RESPONSE (1 << 7) 74 #define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) 75 #define BIT_CMD_DATA_EXPECTED (1 << 9) 76 #define BIT_CMD_READ (0 << 10) 77 #define BIT_CMD_WRITE (1 << 10) 78 #define BIT_CMD_BLOCK_TRANSFER (0 << 11) 79 #define BIT_CMD_STREAM_TRANSFER (1 << 11) 80 #define BIT_CMD_SEND_AUTO_STOP (1 << 12) 81 #define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 82 #define BIT_CMD_STOP_ABORT_CMD (1 << 14) 83 #define BIT_CMD_SEND_INIT (1 << 15) 84 #define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) 85 #define BIT_CMD_READ_CEATA_DEVICE (1 << 22) 86 #define BIT_CMD_CCS_EXPECTED (1 << 23) 87 #define BIT_CMD_ENABLE_BOOT (1 << 24) 88 #define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) 89 #define BIT_CMD_DISABLE_BOOT (1 << 26) 90 #define BIT_CMD_MANDATORY_BOOT (0 << 27) 91 #define BIT_CMD_ALTERNATE_BOOT (1 << 27) 92 #define BIT_CMD_VOLT_SWITCH (1 << 28) 93 #define BIT_CMD_USE_HOLD_REG (1 << 29) 94 #define BIT_CMD_START (1 << 31) 95 96 #define MMC_INT_EBE (1 << 15) /* End-bit Err */ 97 #define MMC_INT_SBE (1 << 13) /* Start-bit Err */ 98 #define MMC_INT_HLE (1 << 12) /* Hardware-lock Err */ 99 #define MMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ 100 #define MMC_INT_DRT (1 << 9) /* Data timeout */ 101 #define MMC_INT_RTO (1 << 8) /* Response timeout */ 102 #define MMC_INT_DCRC (1 << 7) /* Data CRC err */ 103 #define MMC_INT_RCRC (1 << 6) /* Response CRC err */ 104 #define MMC_INT_RXDR (1 << 5) 105 #define MMC_INT_TXDR (1 << 4) 106 #define MMC_INT_DTO (1 << 3) /* Data trans over */ 107 #define MMC_INT_CMD_DONE (1 << 2) 108 #define MMC_INT_RE (1 << 1) 109 110 #define EMMC_FIX_RCA 6 111 112 /* bits in MMC0_CTRL */ 113 #define MMC_CTRL_RESET (1 << 0) 114 #define MMC_FIFO_RESET (1 << 1) 115 #define MMC_DMA_RESET (1 << 2) 116 #define MMC_INT_EN (1 << 4) 117 #define MMC_DMA_EN (1 << 25) 118 119 #define MMC_STS_DATA_BUSY (1 << 9) 120 121 #define MMC_STATUS_CURRENT_STATE_MASK (0xf << 9) 122 #define MMC_STATUS_CURRENT_STATE_SHIFT 9 123 #define MMC_STATUS_READY_FOR_DATA (1 << 8) 124 #define MMC_STATUS_SWITCH_ERROR (1 << 7) 125 126 #define MMC_STATE_IDLE 0 127 #define MMC_STATE_READY 1 128 #define MMC_STATE_IDENT 2 129 #define MMC_STATE_STBY 3 130 #define MMC_STATE_TRAN 4 131 #define MMC_STATE_DATA 5 132 #define MMC_STATE_RCV 6 133 #define MMC_STATE_PRG 7 134 #define MMC_STATE_DIS 8 135 #define MMC_STATE_BTST 9 136 #define MMC_STATE_SLP 10 137 138 #define EXT_CSD_CACHE_CTRL 33 139 #define EXT_CSD_PARTITION_CONFIG 179 140 141 #define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3) 142 #define PART_CFG_PARTITION1_ACCESS (1 << 0) 143 144 #define MMC_IDMAC_ENABLE (1 << 7) 145 #define MMC_IDMAC_FB (1 << 1) 146 #define MMC_IDMAC_SWRESET (1 << 0) 147 148 #define MMC_FIFO_TWMARK(x) (x & 0xfff) 149 #define MMC_FIFO_RWMARK(x) ((x & 0x1ff) << 16) 150 #define MMC_DMA_BURST_SIZE(x) ((x & 0x7) << 28) 151 152 #define MMC_CARD_RD_THR(x) ((x & 0xfff) << 16) 153 #define MMC_CARD_RD_THR_EN (1 << 0) 154 155 extern int init_mmc(void); 156 extern int mmc0_read(unsigned long, size_t, unsigned long, uint32_t); 157 extern int mmc0_write(unsigned long, size_t, unsigned long, uint32_t); 158 159 #endif /* __DW_MMC_H */ 160
