1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by 2 // combiner ------*- C++ -*-===// 3 // 4 // The LLVM Compiler Infrastructure 5 // 6 // This file is distributed under the University of Illinois Open Source 7 // License. See LICENSE.TXT for details. 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 // This file defines instruction pattern supported by combiner 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 16 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 17 18 namespace llvm { 19 20 /// These are instruction patterns matched by the machine combiner pass. 21 enum class MachineCombinerPattern { 22 // These are commutative variants for reassociating a computation chain. See 23 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp. 24 REASSOC_AX_BY, 25 REASSOC_AX_YB, 26 REASSOC_XA_BY, 27 REASSOC_XA_YB, 28 29 // These are multiply-add patterns matched by the AArch64 machine combiner. 30 MULADDW_OP1, 31 MULADDW_OP2, 32 MULSUBW_OP1, 33 MULSUBW_OP2, 34 MULADDWI_OP1, 35 MULSUBWI_OP1, 36 MULADDX_OP1, 37 MULADDX_OP2, 38 MULSUBX_OP1, 39 MULSUBX_OP2, 40 MULADDXI_OP1, 41 MULSUBXI_OP1, 42 // Floating Point 43 FMULADDS_OP1, 44 FMULADDS_OP2, 45 FMULSUBS_OP1, 46 FMULSUBS_OP2, 47 FMULADDD_OP1, 48 FMULADDD_OP2, 49 FMULSUBD_OP1, 50 FMULSUBD_OP2, 51 FMLAv1i32_indexed_OP1, 52 FMLAv1i32_indexed_OP2, 53 FMLAv1i64_indexed_OP1, 54 FMLAv1i64_indexed_OP2, 55 FMLAv2f32_OP2, 56 FMLAv2f32_OP1, 57 FMLAv2f64_OP1, 58 FMLAv2f64_OP2, 59 FMLAv2i32_indexed_OP1, 60 FMLAv2i32_indexed_OP2, 61 FMLAv2i64_indexed_OP1, 62 FMLAv2i64_indexed_OP2, 63 FMLAv4f32_OP1, 64 FMLAv4f32_OP2, 65 FMLAv4i32_indexed_OP1, 66 FMLAv4i32_indexed_OP2, 67 FMLSv1i32_indexed_OP2, 68 FMLSv1i64_indexed_OP2, 69 FMLSv2i32_indexed_OP2, 70 FMLSv2i64_indexed_OP2, 71 FMLSv2f32_OP2, 72 FMLSv2f64_OP2, 73 FMLSv4i32_indexed_OP2, 74 FMLSv4f32_OP2 75 }; 76 77 } // end namespace llvm 78 79 #endif 80
