1 /** 2 3 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved 4 5 This program and the accompanying materials are licensed and made available under 6 the terms and conditions of the BSD License that accompanies this distribution. 7 The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php. 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 14 15 @file 16 PchRegsPcie.h 17 18 @brief 19 Register names for VLV PCI-E root port devices 20 21 Conventions: 22 23 - Prefixes: 24 Definitions beginning with "R_" are registers 25 Definitions beginning with "B_" are bits within registers 26 Definitions beginning with "V_" are meaningful values of bits within the registers 27 Definitions beginning with "S_" are register sizes 28 Definitions beginning with "N_" are the bit position 29 - In general, PCH registers are denoted by "_PCH_" in register names 30 - Registers / bits that are different between PCH generations are denoted by 31 "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_" 32 - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" 33 at the end of the register/bit names 34 - Registers / bits of new devices introduced in a PCH generation will be just named 35 as "_PCH_" without <generation_name> inserted. 36 37 --*/ 38 #ifndef _PCH_REGS_PCIE_H_ 39 #define _PCH_REGS_PCIE_H_ 40 41 #define PCH_PCIE_MAX_ROOT_PORTS 4 42 43 /// 44 /// VLV PCI Express Root Ports (D28:F0~F3) 45 /// 46 #define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 47 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 48 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 49 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 50 #define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 51 52 #define R_PCH_PCIE_ID 0x00 // Identifiers 53 #define B_PCH_PCIE_ID_DID 0xFFFF0000 // Device ID 54 #define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1 55 #define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2 56 #define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3 57 #define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4 58 #define B_PCH_PCIE_ID_VID 0x0000FFFF // Vendor ID 59 #define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID 60 61 62 #define R_PCH_PCIE_BNUM_SLT 0x18 // Bus Numbers; Secondary Latency Timer 63 #define B_PCH_PCIE_BNUM_SLT_SLT 0xFF000000 // Secondary Latency Timer 64 #define B_PCH_PCIE_BNUM_SLT_SBBN 0x00FF0000 // Subordinate Bus Number 65 #define B_PCH_PCIE_BNUM_SLT_SCBN 0x0000FF00 // Secondary Bus Number 66 #define B_PCH_PCIE_BNUM_SLT_PBN 0x000000FF // Primary Bus Number 67 #define R_PCH_PCIE_CAPP 0x34 // Capabilities List Pointer 68 #define B_PCH_PCIE_CAPP 0xFF // Capabilities Pointer 69 70 #define R_PCH_PCIE_SLCTL_SLSTS 0x58 // Slot Control; Slot Status 71 #define S_PCH_PCIE_SLCTL_SLSTS 4 72 #define B_PCH_PCIE_SLCTL_SLSTS_DLLSC BIT24 // Data Link Layer State Changed 73 #define B_PCH_PCIE_SLCTL_SLSTS_PDS BIT22 // Presence Detect State 74 #define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State 75 #define B_PCH_PCIE_SLCTL_SLSTS_PDC BIT19 // Presence Detect Changed 76 #define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed 77 #define B_PCH_PCIE_SLCTL_SLSTS_PFD BIT17 // Power Fault Detected 78 #define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE BIT12 // Data Link Layer State Changed Enable 79 #define B_PCH_PCIE_SLCTL_SLSTS_PCC BIT10 // Power Controller Control 80 #define B_PCH_PCIE_SLCTL_SLSTS_HPE BIT5 // Hot Plug Interrupt Enable 81 #define B_PCH_PCIE_SLCTL_SLSTS_CCE BIT4 // Command Completed Interrupt Enable 82 #define B_PCH_PCIE_SLCTL_SLSTS_PDE BIT3 // Presence Detect Changed Enable 83 84 #define R_PCH_PCIE_SVID 0x94 // Subsystem Vendor IDs 85 #define S_PCH_PCIE_SVID 4 86 #define B_PCH_PCIE_SVID_SID 0xFFFF0000 // Subsystem Identifier 87 #define B_PCH_PCIE_SVID_SVID 0x0000FFFF // Subsystem Vendor Identifier 88 89 #endif 90
