1 /* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _HWR_H_ 18 #define _HWR_H_ 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 #include <stdint.h> 25 #include <stdbool.h> 26 #include <plat/rtc.h> 27 28 /* busses */ 29 #define PERIPH_BUS_AHB1 0 30 #define PERIPH_BUS_AHB2 1 31 #define PERIPH_BUS_AHB3 2 32 #define PERIPH_BUS_APB1 3 33 #define PERIPH_BUS_APB2 4 34 35 36 /* AHB 1 peripherals */ 37 #define PERIPH_AHB1_GPIOA 0x00000001UL 38 #define PERIPH_AHB1_GPIOB 0x00000002UL 39 #define PERIPH_AHB1_GPIOC 0x00000004UL 40 #define PERIPH_AHB1_GPIOD 0x00000008UL 41 #define PERIPH_AHB1_GPIOE 0x00000010UL 42 #define PERIPH_AHB1_GPIOF 0x00000020UL 43 #define PERIPH_AHB1_GPIOG 0x00000040UL 44 #define PERIPH_AHB1_GPIOH 0x00000080UL 45 #define PERIPH_AHB1_GPIOI 0x00000100UL 46 #define PERIPH_AHB1_CRC 0x00001000UL 47 #define PERIPH_AHB1_FLITF 0x00008000UL 48 #define PERIPH_AHB1_SRAM1 0x00010000UL 49 #define PERIPH_AHB1_SRAM2 0x00020000UL 50 #define PERIPH_AHB1_BKPSRAM 0x00040000UL 51 #define PERIPH_AHB1_SRAM3 0x00080000UL 52 #define PERIPH_AHB1_CCMDATARAMEN 0x00100000UL 53 #define PERIPH_AHB1_DMA1 0x00200000UL 54 #define PERIPH_AHB1_DMA2 0x00400000UL 55 #define PERIPH_AHB1_ETH_MAC 0x02000000UL 56 #define PERIPH_AHB1_ETH_MAC_TX 0x04000000UL 57 #define PERIPH_AHB1_ETH_MAC_RX 0x08000000UL 58 #define PERIPH_AHB1_ETH_MAC_PTP 0x10000000UL 59 #define PERIPH_AHB1_OTG_HS 0x20000000UL 60 #define PERIPH_AHB1_OTG_HS_ULPI 0x40000000UL 61 62 /* AHB 2 peripherals */ 63 #define PERIPH_AHB2_DCMI 0x00000001UL 64 #define PERIPH_AHB2_CRYP 0x00000010UL 65 #define PERIPH_AHB2_HASH 0x00000020UL 66 #define PERIPH_AHB2_RNG 0x00000040UL 67 #define PERIPH_AHB2_OTG_FS 0x00000080UL 68 69 /* AHB 3 peripherals */ 70 #define PERIPH_AHB3_FSMC 0x00000001UL 71 72 /* APB 1 peripherals */ 73 #define PERIPH_APB1_TIM2 0x00000001UL 74 #define PERIPH_APB1_TIM3 0x00000002UL 75 #define PERIPH_APB1_TIM4 0x00000004UL 76 #define PERIPH_APB1_TIM5 0x00000008UL 77 #define PERIPH_APB1_TIM6 0x00000010UL 78 #define PERIPH_APB1_TIM7 0x00000020UL 79 #define PERIPH_APB1_TIM12 0x00000040UL 80 #define PERIPH_APB1_TIM13 0x00000080UL 81 #define PERIPH_APB1_TIM14 0x00000100UL 82 #define PERIPH_APB1_WWDG 0x00000800UL 83 #define PERIPH_APB1_SPI2 0x00004000UL 84 #define PERIPH_APB1_SPI3 0x00008000UL 85 #define PERIPH_APB1_USART2 0x00020000UL 86 #define PERIPH_APB1_USART3 0x00040000UL 87 #define PERIPH_APB1_UART4 0x00080000UL 88 #define PERIPH_APB1_UART5 0x00100000UL 89 #define PERIPH_APB1_I2C1 0x00200000UL 90 #define PERIPH_APB1_I2C2 0x00400000UL 91 #define PERIPH_APB1_I2C3 0x00800000UL 92 #define PERIPH_APB1_CAN1 0x02000000UL 93 #define PERIPH_APB1_CAN2 0x04000000UL 94 #define PERIPH_APB1_PWR 0x10000000UL 95 #define PERIPH_APB1_DAC 0x20000000UL 96 #define PERIPH_APB1_UART7 0x40000000UL 97 #define PERIPH_APB1_UART8 0x80000000UL 98 99 /* APB 2 peripherals */ 100 #define PERIPH_APB2_TIM1 0x00000001UL 101 #define PERIPH_APB2_TIM8 0x00000002UL 102 #define PERIPH_APB2_USART1 0x00000010UL 103 #define PERIPH_APB2_USART6 0x00000020UL 104 #define PERIPH_APB2_ADC 0x00000100UL 105 #define PERIPH_APB2_ADC1 0x00000100UL 106 #define PERIPH_APB2_ADC2 0x00000200UL 107 #define PERIPH_APB2_ADC3 0x00000400UL 108 #define PERIPH_APB2_SDIO 0x00000800UL 109 #define PERIPH_APB2_SPI1 0x00001000UL 110 #define PERIPH_APB2_SPI4 0x00002000UL 111 #define PERIPH_APB2_SYSCFG 0x00004000UL 112 #define PERIPH_APB2_TIM9 0x00010000UL 113 #define PERIPH_APB2_TIM10 0x00020000UL 114 #define PERIPH_APB2_TIM11 0x00040000UL 115 #define PERIPH_APB2_SPI5 0x00100000UL 116 #define PERIPH_APB2_SPI6 0x00200000UL 117 118 119 120 121 /* base addrs */ 122 #define UDID_BASE 0x1FFF7A10UL 123 #define TIM2_BASE 0x40000000UL 124 #define TIM3_BASE 0x40000400UL 125 #define TIM4_BASE 0x40000800UL 126 #define TIM5_BASE 0x40000C00UL 127 #define RTC_BASE 0x40002800UL 128 #define WWDG_BASE 0x40002C00UL 129 #define IWDG_BASE 0x40003000UL 130 #define SPI2_BASE 0x40003800UL 131 #define SPI3_BASE 0x40003C00UL 132 #define USART2_BASE 0x40004400UL 133 #define USART3_BASE 0x40004800UL 134 #define UART4_BASE 0x40004C00UL 135 #define UART5_BASE 0x40005000UL 136 #define I2C1_BASE 0x40005400UL 137 #define I2C2_BASE 0x40005800UL 138 #define I2C3_BASE 0x40005C00UL 139 #define PWR_BASE 0x40007000UL 140 #define TIM1_BASE 0x40010000UL 141 #define USART1_BASE 0x40011000UL 142 #define USART6_BASE 0x40011400UL 143 #define SPI1_BASE 0x40013000UL 144 #define SPI4_BASE 0x40013400UL 145 #define SYSCFG_BASE 0x40013800UL 146 #define EXTI_BASE 0x40013C00UL 147 #define TIM9_BASE 0x40014000UL 148 #define TIM10_BASE 0x40014400UL 149 #define TIM11_BASE 0x40014800UL 150 #define SPI5_BASE 0x40015000UL 151 #define SPI6_BASE 0x40015400UL 152 #define GPIOA_BASE 0x40020000UL 153 #define GPIOB_BASE 0x40020400UL 154 #define GPIOC_BASE 0x40020800UL 155 #define GPIOD_BASE 0x40020C00UL 156 #define GPIOE_BASE 0x40021000UL 157 #define GPIOF_BASE 0x40021400UL 158 #define GPIOG_BASE 0x40021800UL 159 #define GPIOH_BASE 0x40021C00UL 160 #define GPIOI_BASE 0x40022000UL 161 #define CRC_BASE 0x40023000UL 162 #define RCC_BASE 0x40023800UL 163 #define FLASH_BASE 0x40023C00UL 164 #define DMA1_BASE 0x40026000UL 165 #define DMA2_BASE 0x40026400UL 166 #define DBG_BASE 0xE0042000UL 167 168 169 enum Stm32F4xxSleepType { //current power wkup way wkup speed (typ/max) 170 stm32f411SleepModeSleep, //2.7-5.9mA all-core interrupt 1 cy 171 stm32f411SleepModeStopMR, //111uA RTC,flash,reg EXTI 13.5/14.5us 172 stm32f411SleepModeStopMRFPD,// 73uA RTC,reg EXTI 105/111us 173 stm32f411SleepModeStopLPFD, // 42uA RTC,lpreg EXTI 113/130us 174 stm32f411SleepModeStopLPLV, // 10uA RTC EXTT 314/407us (actually lower, but not quoted) 175 }; 176 177 /* funcs */ 178 void pwrSystemInit(void); 179 uint32_t pwrResetReason(void); 180 void pwrUnitClock(uint32_t bus, uint32_t unit, bool on); 181 void pwrUnitReset(uint32_t bus, uint32_t unit, bool on); 182 uint32_t pwrGetBusSpeed(uint32_t bus); 183 void pwrEnableAndClockRtc(enum RtcClock); 184 void pwrEnableWriteBackupDomainRegs(void); 185 186 /* internal to platform */ 187 void pwrSetSleepType(enum Stm32F4xxSleepType sleepType); 188 189 #ifdef __cplusplus 190 } 191 #endif 192 193 #endif 194 195
