1 /* 2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved. 3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * Neither the name of ARM nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific 17 * prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __HIKEY_DEF_H__ 33 #define __HIKEY_DEF_H__ 34 35 #define DEVICE_BASE 0xf4000000 36 #define DEVICE_SIZE 0x05800000 37 38 /* The size of DDR RAM is 1GB. */ 39 #define DRAM_BASE 0x00000000 40 #define DRAM_SIZE 0x40000000 41 42 #define XG2RAM0_BASE 0xF9800000 43 #define XG2RAM0_SIZE 0x00400000 44 45 #define PLAT_TRUSTED_SRAM_ID 0 46 #define PLAT_TRUSTED_DRAM_ID 1 47 48 /* 49 * DRAM at 0x0000_0000 is divided in two regions: 50 * - Secure DRAM (default is the top 16MB) 51 * - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE) 52 */ 53 #define DRAM_SEC_SIZE 0x01000000 54 #define DRAM_SEC_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SEC_SIZE) 55 56 #define DRAM_NS_BASE DRAM_BASE 57 #define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SEC_SIZE) 58 59 #define SRAM_BASE 0xFFF80000 60 #define SRAM_SIZE 0x00012000 61 62 /******************************************************************************* 63 * GIC-400 & interrupt handling related constants 64 ******************************************************************************/ 65 #define GICD_BASE 0xF6801000 66 #define GICC_BASE 0xF6802000 67 68 #define IRQ_SEC_PHY_TIMER 29 69 #define IRQ_SEC_SGI_0 8 70 #define IRQ_SEC_SGI_1 9 71 #define IRQ_SEC_SGI_2 10 72 #define IRQ_SEC_SGI_3 11 73 #define IRQ_SEC_SGI_4 12 74 #define IRQ_SEC_SGI_5 13 75 #define IRQ_SEC_SGI_6 14 76 #define IRQ_SEC_SGI_7 15 77 #define IRQ_SEC_SGI_8 16 78 79 /******************************************************************************* 80 * PL011 related constants 81 ******************************************************************************/ 82 #define PL011_UART0_BASE 0xF8015000 83 #define PL011_UART3_BASE 0xF7113000 84 85 #define PL011_BAUDRATE 115200 86 87 #define PL011_UART_CLK_IN_HZ 19200000 88 89 /******************************************************************************* 90 * CCI-400 related constants 91 ******************************************************************************/ 92 #define CCI400_BASE 0xF6E90000 93 #define CCI400_SL_IFACE3_CLUSTER_IX 0 94 #define CCI400_SL_IFACE4_CLUSTER_IX 1 95 96 #endif /* __HIKEY_DEF_H__ */ 97
