1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __JUNO_DEF_H__ 32 #define __JUNO_DEF_H__ 33 34 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 35 #define JUNO_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 36 37 /******************************************************************************* 38 * Juno memory map related constants 39 ******************************************************************************/ 40 #define FLASH_BASE 0x08000000 41 #define FLASH_SIZE 0x04000000 42 43 /* Bypass offset from start of NOR flash */ 44 #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 45 46 #ifndef TZROM_BASE 47 /* Use the bypass address */ 48 #define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET 49 #endif 50 /* Actual ROM size on Juno is 64 KB, but TBB requires at least 80 KB in debug 51 * mode. We can test TBB on Juno bypassing the ROM and using 128 KB of flash */ 52 #if TRUSTED_BOARD_BOOT 53 #define TZROM_SIZE 0x00020000 54 #else 55 #define TZROM_SIZE 0x00010000 56 #endif 57 58 #define TZRAM_BASE 0x04001000 59 #define TZRAM_SIZE 0x0003F000 60 61 #define PLAT_TRUSTED_SRAM_ID 0 62 #define PLAT_DRAM_ID 1 63 64 #define MHU_SECURE_BASE 0x04000000 65 #define MHU_SECURE_SIZE 0x00001000 66 67 #define MHU_PAYLOAD_CACHED 0 68 69 #define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE 70 #define TRUSTED_MAILBOX_SHIFT 4 71 72 #define EMMC_BASE 0x0c000000 73 #define EMMC_SIZE 0x04000000 74 75 #define PSRAM_BASE 0x14000000 76 #define PSRAM_SIZE 0x02000000 77 78 #define IOFPGA_BASE 0x1c000000 79 #define IOFPGA_SIZE 0x03000000 80 81 #define NSROM_BASE 0x1f000000 82 #define NSROM_SIZE 0x00001000 83 84 /* Following covers Columbus Peripherals excluding NSROM and NSRAM */ 85 #define DEVICE0_BASE 0x20000000 86 #define DEVICE0_SIZE 0x0e000000 87 #define MHU_BASE 0x2b1f0000 88 89 #define NSRAM_BASE 0x2e000000 90 #define NSRAM_SIZE 0x00008000 91 92 /* Following covers Juno Peripherals and PCIe expansion area */ 93 #define DEVICE1_BASE 0x40000000 94 #define DEVICE1_SIZE 0x40000000 95 #define PCIE_CONTROL_BASE 0x7ff20000 96 97 #define DRAM_BASE 0x80000000 98 #define DRAM_SIZE 0x80000000 99 100 /* 101 * DRAM at 0x8000_0000 is divided in two regions: 102 * - Secure DRAM (default is the top 16MB except for the last 2MB, which are 103 * used by the SCP for DDR retraining) 104 * - Non-Secure DRAM (remaining DRAM starting at DRAM_BASE) 105 */ 106 107 #define DRAM_SCP_SIZE 0x00200000 108 #define DRAM_SCP_BASE (DRAM_BASE + DRAM_SIZE - DRAM_SCP_SIZE) 109 110 #define DRAM_SEC_SIZE 0x00E00000 111 #define DRAM_SEC_BASE (DRAM_SCP_BASE - DRAM_SEC_SIZE) 112 113 #define DRAM_NS_BASE DRAM_BASE 114 #define DRAM_NS_SIZE (DRAM_SIZE - DRAM_SCP_SIZE - DRAM_SEC_SIZE) 115 116 /* Second region of DRAM */ 117 #define DRAM2_BASE 0x880000000 118 #define DRAM2_SIZE 0x180000000 119 120 /* Memory mapped Generic timer interfaces */ 121 #define SYS_CNTCTL_BASE 0x2a430000 122 #define SYS_CNTREAD_BASE 0x2a800000 123 #define SYS_TIMCTL_BASE 0x2a810000 124 125 /* V2M motherboard system registers & offsets */ 126 #define VE_SYSREGS_BASE 0x1c010000 127 #define V2M_SYS_LED 0x8 128 129 /* 130 * V2M sysled bit definitions. The values written to this 131 * register are defined in arch.h & runtime_svc.h. Only 132 * used by the primary cpu to diagnose any cold boot issues. 133 * 134 * SYS_LED[0] - Security state (S=0/NS=1) 135 * SYS_LED[2:1] - Exception Level (EL3-EL0) 136 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 137 * 138 */ 139 #define SYS_LED_SS_SHIFT 0x0 140 #define SYS_LED_EL_SHIFT 0x1 141 #define SYS_LED_EC_SHIFT 0x3 142 143 /******************************************************************************* 144 * GIC-400 & interrupt handling related constants 145 ******************************************************************************/ 146 #define GICD_BASE 0x2c010000 147 #define GICC_BASE 0x2c02f000 148 #define GICH_BASE 0x2c04f000 149 #define GICV_BASE 0x2c06f000 150 151 #define IRQ_MHU 69 152 #define IRQ_GPU_SMMU_0 71 153 #define IRQ_GPU_SMMU_1 73 154 #define IRQ_ETR_SMMU 75 155 #define IRQ_TZC400 80 156 #define IRQ_TZ_WDOG 86 157 158 #define IRQ_SEC_PHY_TIMER 29 159 #define IRQ_SEC_SGI_0 8 160 #define IRQ_SEC_SGI_1 9 161 #define IRQ_SEC_SGI_2 10 162 #define IRQ_SEC_SGI_3 11 163 #define IRQ_SEC_SGI_4 12 164 #define IRQ_SEC_SGI_5 13 165 #define IRQ_SEC_SGI_6 14 166 #define IRQ_SEC_SGI_7 15 167 168 /******************************************************************************* 169 * PL011 related constants 170 ******************************************************************************/ 171 /* FPGA UART0 */ 172 #define PL011_UART0_BASE 0x1c090000 173 /* FPGA UART1 */ 174 #define PL011_UART1_BASE 0x1c0a0000 175 /* SoC UART0 */ 176 #define PL011_UART2_BASE 0x7ff80000 177 /* SoC UART1 */ 178 #define PL011_UART3_BASE 0x7ff70000 179 180 #define PL011_BAUDRATE 115200 181 182 #define PL011_UART0_CLK_IN_HZ 24000000 183 #define PL011_UART1_CLK_IN_HZ 24000000 184 #define PL011_UART2_CLK_IN_HZ 7273800 185 #define PL011_UART3_CLK_IN_HZ 7273800 186 187 /******************************************************************************* 188 * NIC-400 related constants 189 ******************************************************************************/ 190 191 /* CSS NIC-400 Global Programmers View (GPV) */ 192 #define CSS_NIC400_BASE 0x2a000000 193 194 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 195 #define CSS_NIC400_SLAVE_BOOTSECURE 8 196 197 /* SoC NIC-400 Global Programmers View (GPV) */ 198 #define SOC_NIC400_BASE 0x7fd00000 199 200 #define SOC_NIC400_USB_EHCI 0 201 #define SOC_NIC400_TLX_MASTER 1 202 #define SOC_NIC400_USB_OHCI 2 203 #define SOC_NIC400_PL354_SMC 3 204 /* 205 * The apb4_bridge controls access to: 206 * - the PCIe configuration registers 207 * - the MMU units for USB, HDLCD and DMA 208 */ 209 #define SOC_NIC400_APB4_BRIDGE 4 210 /* 211 * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 212 */ 213 #define SOC_NIC400_BOOTSEC_BRIDGE 5 214 #define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) 215 216 /******************************************************************************* 217 * TZC-400 related constants 218 ******************************************************************************/ 219 #define TZC400_BASE 0x2a4a0000 220 221 #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ 222 #define TZC400_NSAID_PCIE 1 223 #define TZC400_NSAID_HDLCD0 2 224 #define TZC400_NSAID_HDLCD1 3 225 #define TZC400_NSAID_USB 4 226 #define TZC400_NSAID_DMA330 5 227 #define TZC400_NSAID_THINLINKS 6 228 #define TZC400_NSAID_AP 9 229 #define TZC400_NSAID_GPU 10 230 #define TZC400_NSAID_SCP 11 231 #define TZC400_NSAID_CORESIGHT 12 232 233 /******************************************************************************* 234 * CCI-400 related constants 235 ******************************************************************************/ 236 #define CCI400_BASE 0x2c090000 237 #define CCI400_SL_IFACE3_CLUSTER_IX 1 238 #define CCI400_SL_IFACE4_CLUSTER_IX 0 239 240 /******************************************************************************* 241 * SCP <=> AP boot configuration 242 ******************************************************************************/ 243 #define SCP_BOOT_CFG_ADDR 0x04000080 244 #define PRIMARY_CPU_SHIFT 8 245 #define PRIMARY_CPU_MASK 0xf 246 247 #endif /* __JUNO_DEF_H__ */ 248
