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Searched
defs:RegBank
(Results
1 - 8
of
8
) sorted by null
/external/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBankInfo.h
54
const RegisterBank *
RegBank
;
60
const RegisterBank &
RegBank
)
61
: StartIdx(StartIdx), Length(Length),
RegBank
(&
RegBank
) {}
73
/// Check that the Mask is compatible with the
RegBank
.
74
/// Indeed, if the
RegBank
cannot accomadate the "active bits" of the mask,
166
/// This element will map to \p
RegBank
and fully define a mask, whose
169
const RegisterBank &
RegBank
);
363
/// Record \p
RegBank
as the register bank that covers \p SVT.
368
/// getRegBankForType(SVT) == &
RegBank
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all
...]
/external/llvm/lib/CodeGen/GlobalISel/
RegisterBankInfo.cpp
48
const RegisterBank &
RegBank
= getRegBank(Idx);
49
assert(Idx ==
RegBank
.getID() &&
51
dbgs() << "Verify " <<
RegBank
<< '\n';
52
assert(
RegBank
.verify(TRI) && "
RegBank
is invalid");
60
RegisterBank &
RegBank
= getRegBank(ID);
61
assert(
RegBank
.getID() == RegisterBank::InvalidID &&
63
RegBank
.ID = ID;
64
RegBank
.Name = Name;
195
const RegisterBank &
RegBank
= getRegBankFromRegClass(*RC)
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...]
/external/llvm/utils/TableGen/
CodeGenTarget.h
70
mutable std::unique_ptr<CodeGenRegBank>
RegBank
;
RegisterInfoEmitter.cpp
77
void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &
RegBank
,
79
void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &
RegBank
,
81
void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &
RegBank
,
190
EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &
RegBank
,
192
unsigned NumRCs =
RegBank
.getRegClasses().size();
193
unsigned NumSets =
RegBank
.getNumRegPressureSets();
199
for (const auto &RC :
RegBank
.getRegClasses()) {
206
OS << " {" << (*Regs.begin())->getWeight(
RegBank
)
207
<< ", " <<
RegBank
.getRegUnitSetWeight(RegUnits);
218
for (unsigned UnitIdx = 0, UnitEnd =
RegBank
.getNumNativeRegUnits()
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...]
/external/swiftshader/third_party/LLVM/utils/TableGen/
CodeGenTarget.h
68
mutable CodeGenRegBank *
RegBank
;
RegisterInfoEmitter.cpp
243
CodeGenRegBank &
RegBank
) {
250
RegBank
.computeOverlaps(Overlaps);
262
const std::vector<CodeGenRegister*> &Regs =
RegBank
.getRegisters();
333
ArrayRef<CodeGenRegisterClass*> RegisterClasses =
RegBank
.getRegClasses();
407
CodeGenRegBank &
RegBank
) {
433
const std::vector<Record*> &SubRegIndices =
RegBank
.getSubRegIndices();
440
for (unsigned i = 0, e =
RegBank
.getNumNamedIndices(); i != e; ++i)
448
ArrayRef<CodeGenRegisterClass*> RegisterClasses =
RegBank
.getRegClasses();
483
CodeGenRegBank &
RegBank
){
496
ArrayRef<CodeGenRegisterClass*> RegisterClasses =
RegBank
.getRegClasses()
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...]
/external/llvm/lib/CodeGen/MIRParser/
MIRParser.cpp
380
const auto *
RegBank
= getRegBank(MF, VReg.Class.Value);
381
if (!
RegBank
)
387
RegInfo.setRegBank(Reg, *
RegBank
);
736
const auto &
RegBank
= RBI->getRegBank(I);
738
std::make_pair(StringRef(
RegBank
.getName()).lower(), &
RegBank
));
/external/llvm/lib/CodeGen/
MachineVerifier.cpp
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...]
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